📄 chen2.txt
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module ddd(clk,rst,dout,ce,outd);
input clk;
input rst;
output [6:0]dout;
output [3:0]ce;
output outd;
reg[6:0]dout;
reg[3:0]led1;
reg[3:0]led2;
reg[3:0]led3;
reg[3:0]led4;
reg[25:0]c;
reg[24:0]c1;
reg[3:0]ce;
reg dian;
reg outd;
always@(posedge clk)
begin
if(!rst)begin
led1<=0;
led2<=0;
led3<=0;
led4<=0;
c<=0;
dian<=0;
end
else if(c<5000_0000)c<=c+1;
else begin
dian<=~dian;
c<=0;
if(led3==5&&led4==9)
begin
led3<=0;
led4<=0;
if(led2<9)led2<=led2+1;
else if(led1==5&&led2==9)begin
led1<=0;
led2<=0;
end
else begin
led2<=0;
led1<=led1+1;
end
end
else begin
if(led4<9)led4<=led4+1;
else begin
led4<=0;
led3<=led3+1;
end
end
end
end
always@(posedge clk)
begin if(!rst)begin
dout<=0;
c1<=0;
ce<=4'b1011; outd<=0;
end
else if(ce==4'b1011)
begin
if(c1<10_0000)c1<=c1+1;
else
begin
ce<=4'b1101; outd<=0;
c1<=0;
case(led3)
0:dout<=7'b011_1111;
1:dout<=7'b000_0110;
2:dout<=7'b101_1011;
3:dout<=7'b100_1111;
4:dout<=7'b110_0110;
5:dout<=7'b110_1101;
default:dout<=7'b000_1111;
endcase
end
end
else if(ce==4'b1101)
begin
if(c1<10_0000)c1<=c1+1;
else
begin
ce<=4'b1110; outd<=0;
c1<=0;
case(led4)
0:dout<=7'b011_1111;
1:dout<=7'b000_0110;
2:dout<=7'b101_1011;
3:dout<=7'b100_1111;
4:dout<=7'b110_0110;
5:dout<=7'b110_1101;
6:dout<=7'b111_1101;
7:dout<=7'b000_0111;
8:dout<=7'b111_1111;
9:dout<=7'b110_1111;
default:dout<=7'b000_0000;
endcase
end
end
else if(ce==4'b1110)
begin
if(c1<10_0000)c1<=c1+1;
else
begin
ce<=4'b0111; outd<=0;
c1<=0;
case(led1)
0:dout<=7'b011_1111;
1:dout<=7'b000_0110;
2:dout<=7'b101_1011;
3:dout<=7'b100_1111;
4:dout<=7'b110_0110;
5:dout<=7'b110_1101;
default:dout<=7'b000_0000;
endcase
end
end
else if(ce==4'b0111)
begin
if(c1<10_0000)c1<=c1+1;
else
begin
ce<=4'b1011;
outd<=dian;
c1<=0;
case(led2)
0:dout<=7'b011_1111;
1:dout<=7'b000_0110;
2:dout<=7'b101_1011;
3:dout<=7'b100_1111;
4:dout<=7'b110_0110;
5:dout<=7'b110_1101;
6:dout<=7'b111_1101;
7:dout<=7'b000_0111;
8:dout<=7'b111_1111;
9:dout<=7'b110_1111;
default:dout<=7'b000_11110;
endcase
end
end
else ce<=ce;
end
endmodule
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