lesson.v

Verilog编写的UART程序源代码。测试成功。支持字符串发送

module	lesson;
	/*
	this uart program include 3 parts . the receive part,send part and speed select part
	the receice part user 3 registers to decide when start receive the data.
	and then use a counter to count how many bits were translated.
	it user a shift_register to receive the data
	when data translate were over.it send a signal to the transmit part
	the transmit then resent the data
	*/
	my_uart_speed(clk,clk_bps,bps_start);
	my_uart_rx(clk,uart_rx,nrst,rev_data,int_signal,clk_bps,start_bps);
	my_uart_tx(clk,uart_tx,nrst,int_singal,clk_bps,rx_data,start_bps);
endmodule