uart.tan.qmsg

Verilog编写的UART程序源代码。测试成功。支持字符串发送

{ "Info" "ITDB_FULL_TPD_RESULT" "rs232_rx altera_auto_signaltap_0_rs232_rx_ae 9.426 ns Longest " "Info: Longest tpd from source pin \"rs232_rx\" to destination pin \"altera_auto_signaltap_0_rs232_rx_ae\" is 9.426 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns rs232_rx 1 PIN PIN_191 5 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_191; Fanout = 5; PIN Node = 'rs232_rx'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs232_rx } "NODE_NAME" } } { "my_uart_top.v" "" { Text "D:/mydesign/uart/my_uart_top.v" 7 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.807 ns) + CELL(0.206 ns) 7.997 ns altera_auto_signaltap_0_rs232_rx_signaltap_lcell 2 COMB LCCOMB_X16_Y9_N4 1 " "Info: 2: + IC(6.807 ns) + CELL(0.206 ns) = 7.997 ns; Loc. = LCCOMB_X16_Y9_N4; Fanout = 1; COMB Node = 'altera_auto_signaltap_0_rs232_rx_signaltap_lcell'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.013 ns" { rs232_rx altera_auto_signaltap_0_rs232_rx_signaltap_lcell } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.429 ns) + CELL(0.000 ns) 9.426 ns altera_auto_signaltap_0_rs232_rx_ae 3 PIN LCCOMB_X18_Y10_N0 0 " "Info: 3: + IC(1.429 ns) + CELL(0.000 ns) = 9.426 ns; Loc. = LCCOMB_X18_Y10_N0; Fanout = 0; PIN Node = 'altera_auto_signaltap_0_rs232_rx_ae'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.429 ns" { altera_auto_signaltap_0_rs232_rx_signaltap_lcell altera_auto_signaltap_0_rs232_rx_ae } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.190 ns ( 12.62 % ) " "Info: Total cell delay = 1.190 ns ( 12.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.236 ns ( 87.38 % ) " "Info: Total interconnect delay = 8.236 ns ( 87.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.426 ns" { rs232_rx altera_auto_signaltap_0_rs232_rx_signaltap_lcell altera_auto_signaltap_0_rs232_rx_ae } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "9.426 ns" { rs232_rx {} rs232_rx~combout {} altera_auto_signaltap_0_rs232_rx_signaltap_lcell {} altera_auto_signaltap_0_rs232_rx_ae {} } { 0.000ns 0.000ns 6.807ns 1.429ns } { 0.000ns 0.984ns 0.206ns 0.000ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\] altera_internal_jtag~TDIUTAP altera_internal_jtag~TCKUTAP 2.009 ns register " "Info: th for register \"sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\]\" (data pin = \"altera_internal_jtag~TDIUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 2.009 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.387 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.387 ns" { { "In