prev_cmp_uart.map.qmsg

Verilog编写的UART程序源代码。测试成功。支持字符串发送

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "speed_select:speed_select\|bps_para_2\[4\] data_in GND " "Warning (14130): Reduced register \"speed_select:speed_select\|bps_para_2\[4\]\" with stuck data_in port to stuck value GND" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 63 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG_PWRUP_DC" "speed_select:speed_select\|bps_para_2\[3\] data_in VCC " "Warning (14131): Reduced register \"speed_select:speed_select\|bps_para_2\[3\]\" with stuck data_in port to stuck value VCC -- power-up level has changed" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 63 -1 0 } }  } 0 14131 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s! -- power-up level has changed" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "speed_select:speed_select\|bps_para_2\[2\] data_in GND " "Warning (14130): Reduced register \"speed_select:speed_select\|bps_para_2\[2\]\" with stuck data_in port to stuck value GND" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 63 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG_PWRUP_DC" "speed_select:speed_select\|bps_para_2\[1\] data_in VCC " "Warning (14131): Reduced register \"speed_select:speed_select\|bps_para_2\[1\]\" with stuck data_in port to stuck value VCC -- power-up level has changed" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 63 -1 0 } }  } 0 14131 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s! -- power-up level has changed" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG_PWRUP_DC" "speed_select:speed_select\|bps_para_2\[0\] data_in VCC " "Warning (14131): Reduced register \"speed_select:speed_select\|bps_para_2\[0\]\" with stuck data_in port to stuck value VCC -- power-up level has changed" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 63 -1 0 } }  } 0 14131 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s! -- power-up level has changed" 0 0 "" 0 0}
{ "Info" "ISGN_RTL_SYNTHESIZE_TOP_PARTITION" "" "Info: Starting High-Level Optimization for Top Partition" {  } {  } 0 0 "Starting High-Level Optimization for Top Partition" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_SELECTOR" "\"bps_start\" " "Warning: Converted tri-state node \"bps_start\" into a selector" {  } {  } 0 0 "Converted tri-state node %1!s! into a selector" 0 0 "" 0 0}  } {  } 0 0 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "" 0 0}
{ "Info" "ISGN_RTL_SYNTHESIZE_PARTITION" "sld_signaltap:auto_signaltap_0 " "Info: Starting High-Level Optimization for Partition sld_signaltap:auto_signaltap_0" {  } {  } 0 0 "Starting High-Level Optimization for Partition %1!s!" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|buffer_write_enable_delayed sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|segment_shift_clk_ena " "Info (13350): Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|buffer_write_enable_delayed\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|segment_shift_clk_ena\"" {  } { { "../../altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "D:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 761 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[0\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[0\] " "Info (13350): Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[0\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[0\]\"" {  } { { "../../altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "D:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[1\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[1\] " "Info (13350): Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[1\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[1\]\"" {  } { { "../../altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "D:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[2\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[2\] " "Info (13350): Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[2\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[2\]\"" {  } { { "../../altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "D:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[3\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[3\] " "Info (13350): Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[3\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[3\]\"" {  } { { "../../altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "D:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[4\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[4\] " "Info (13350): Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[4\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[4\]\"" {  } { { "../../altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "D:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[5\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[5\] " "Info (13350): Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[5\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[5\]\"" {  } { { "../../altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "D:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[6\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[6\] " "Info (13350): Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[6\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[6\]\"" {  } { { "../../altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "D:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0 0}
{ "Info" "ISGN_RTL_SYNTHESIZE_PARTITION" "sld_hub:sld_hub_inst " "Info: Starting High-Level Optimization for Partition sld_hub:sld_hub_inst" {  } {  } 0 0 "Starting High-Level Optimization for Partition %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_RTL_SYNTHESIZE_TOP_PARTITION" "" "Info: Starting High-Level Optimization for Top Partition" {  } {  } 0 0 "Starting High-Level Optimization for Top Partition" 0 0 "" 0 0}
{ "Info" "ISGN_RTL_SYNTHESIZE_PARTITION" "sld_signaltap:auto_signaltap_0 " "Info: Starting High-Level Optimization for Partition sld_signaltap:auto_signaltap_0" {  } {  } 0 0 "Starting High-Level Optimization for Partition %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_RTL_SYNTHESIZE_PARTITION" "sld_hub:sld_hub_inst " "Info: Starting High-Level Optimization for Partition sld_hub:sld_hub_inst" {  } {  } 0 0 "Starting High-Level Optimization for Partition %1!s!" 0 0 "" 0 0}
{ "Info" "IQSYN_SYNTHESIZE_TOP_PARTITION" "" "Info: Starting Logic Optimization and Technology Mapping for Top Partition" {  } {  } 0 0 "Starting Logic Optimization and Technology Mapping for Top Partition" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "my_uart_tx.v" "" { Text "D:/mydesign/uart/my_uart_tx.v" 74 -1 0 } } { "my_uart_rx.v" "" { Text "D:/mydesign/uart/my_uart_rx.v" 13 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 2 " "Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "my_uart_rx:my_uart_rx\|bps_start_r~en " "Info: Register \"my_uart_rx:my_uart_rx\|bps_start_r~en\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "my_uart_tx:my_uart_tx\|bps_start_r~en " "Info: Register \"my_uart_tx:my_uart_tx\|bps_start_r~en\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 0}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Info: Found the following redundant logic cells in design" {  } {  } 0 0 "Found the following redundant logic cells in design" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "98 " "Info: Implemented 98 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "91 " "Info: Implemented 91 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQSYN_SYNTHESIZE_PARTITION" "sld_signaltap:auto_signaltap_0 " "Info: Starting Logic Optimization and Technology Mapping for Partition sld_signaltap:auto_signaltap_0" {  } {  } 0 0 "Starting Logic Optimization and Technology Mapping for Partition %1!s!" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "../../altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "D:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "405 " "Info: Implemented 405 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "61 " "Info: Implemented 61 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "325 " "Info: Implemented 325 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_RAMS" "3 " "Info: Implemented 3 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQSYN_SYNTHESIZE_PARTITION" "sld_hub:sld_hub_inst " "Info: Starting Logic Optimization and Technology Mapping for Partition sld_hub:sld_hub_inst" {  } {  } 0 0 "Starting Logic Optimization and Technology Mapping for Partition %1!s!" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "../../altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "169 " "Info: Implemented 169 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Info: Implemented 18 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Info: Implemented 35 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "116 " "Info: Implemented 116 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 41 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 41 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "196 " "Info: Peak virtual memory: 196 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 05 21:28:51 2009 " "Info: Processing ended: Sun Apr 05 21:28:51 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Info: Elapsed time: 00:00:19" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Info: Total CPU time (on all processors): 00:00:10" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}