prev_cmp_uart.map.qmsg

Verilog编写的UART程序源代码。测试成功。支持字符串发送

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Web Edition " "Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 05 21:28:32 2009 " "Info: Processing started: Sun Apr 05 21:28:32 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off uart -c uart " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart -c uart" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "speed_select.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file speed_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 speed_select " "Info: Found entity 1: speed_select" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "my_uart_rx.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file my_uart_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 my_uart_rx " "Info: Found entity 1: my_uart_rx" {  } { { "my_uart_rx.v" "" { Text "D:/mydesign/uart/my_uart_rx.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "my_uart_tx.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file my_uart_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 my_uart_tx " "Info: Found entity 1: my_uart_tx" {  } { { "my_uart_tx.v" "" { Text "D:/mydesign/uart/my_uart_tx.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "my_uart_top.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file my_uart_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 my_uart_top " "Info: Found entity 1: my_uart_top" {  } { { "my_uart_top.v" "" { Text "D:/mydesign/uart/my_uart_top.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "my_uart_top " "Info: Elaborating entity \"my_uart_top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "speed_select speed_select:speed_select " "Info: Elaborating entity \"speed_select\" for hierarchy \"speed_select:speed_select\"" {  } { { "my_uart_top.v" "speed_select" { Text "D:/mydesign/uart/my_uart_top.v" 20 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 speed_select.v(38) " "Warning (10230): Verilog HDL assignment warning at speed_select.v(38): truncated value with size 32 to match size of target (13)" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 speed_select.v(39) " "Warning (10230): Verilog HDL assignment warning at speed_select.v(39): truncated value with size 32 to match size of target (13)" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 39 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 speed_select.v(42) " "Warning (10230): Verilog HDL assignment warning at speed_select.v(42): truncated value with size 32 to match size of target (13)" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 42 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 speed_select.v(43) " "Warning (10230): Verilog HDL assignment warning at speed_select.v(43): truncated value with size 32 to match size of target (13)" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 43 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 speed_select.v(47) " "Warning (10230): Verilog HDL assignment warning at speed_select.v(47): truncated value with size 32 to match size of target (13)" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 47 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 speed_select.v(48) " "Warning (10230): Verilog HDL assignment warning at speed_select.v(48): truncated value with size 32 to match size of target (13)" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 48 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 speed_select.v(52) " "Warning (10230): Verilog HDL assignment warning at speed_select.v(52): truncated value with size 32 to match size of target (13)" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 52 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 speed_select.v(53) " "Warning (10230): Verilog HDL assignment warning at speed_select.v(53): truncated value with size 32 to match size of target (13)" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 53 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 speed_select.v(57) " "Warning (10230): Verilog HDL assignment warning at speed_select.v(57): truncated value with size 32 to match size of target (13)" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 57 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 speed_select.v(58) " "Warning (10230): Verilog HDL assignment warning at speed_select.v(58): truncated value with size 32 to match size of target (13)" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 58 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "uart_ctrl speed_select.v(31) " "Warning (10240): Verilog HDL Always Construct warning at speed_select.v(31): inferring latch(es) for variable \"uart_ctrl\", which holds its previous value in one or more paths through the always construct" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 31 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "uart_ctrl.100 speed_select.v(31) " "Info (10041): Inferred latch for \"uart_ctrl.100\" at speed_select.v(31)" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 31 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "uart_ctrl.011 speed_select.v(31) " "Info (10041): Inferred latch for \"uart_ctrl.011\" at speed_select.v(31)" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 31 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "uart_ctrl.010 speed_select.v(31) " "Info (10041): Inferred latch for \"uart_ctrl.010\" at speed_select.v(31)" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 31 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "uart_ctrl.001 speed_select.v(31) " "Info (10041): Inferred latch for \"uart_ctrl.001\" at speed_select.v(31)" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 31 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "uart_ctrl.000 speed_select.v(31) " "Info (10041): Inferred latch for \"uart_ctrl.000\" at speed_select.v(31)" {  } { { "speed_select.v" "" { Text "D:/mydesign/uart/speed_select.v" 31 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "my_uart_rx my_uart_rx:my_uart_rx " "Info: Elaborating entity \"my_uart_rx\" for hierarchy \"my_uart_rx:my_uart_rx\"" {  } { { "my_uart_top.v" "my_uart_rx" { Text "D:/mydesign/uart/my_uart_top.v" 30 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "my_uart_tx my_uart_tx:my_uart_tx " "Info: Elaborating entity \"my_uart_tx\" for hierarchy \"my_uart_tx:my_uart_tx\"" {  } { { "my_uart_top.v" "my_uart_tx" { Text "D:/mydesign/uart/my_uart_top.v" 41 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_QIC_SYNTHESIS_TOP_ONE" "" "Info: 1 design partition requires synthesis" { { "Info" "ISGN_QIC_SYNTHESIS_REASON_FILE_CHANGE" "Top " "Info: Partition \"Top\" requires synthesis because there were changes to its dependent source files" {  } {  } 0 0 "Partition \"%1!s!\" requires synthesis because there were changes to its dependent source files" 0 0 "" 0 0}  } {  } 0 0 "1 design partition requires synthesis" 0 0 "" 0 0}
{ "Info" "ISGN_QIC_NO_SYNTHESIS_TOP_ZERO" "" "Info: 0 design partitions will skip synthesis in the current incremental compilation" {  } {  } 0 0 "0 design partitions will skip synthesis in the current incremental compilation" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_g1p3.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_g1p3.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_g1p3 " "Info: Found entity 1: altsyncram_g1p3" {  } { { "db/altsyncram_g1p3.tdf" "" { Text "D:/mydesign/uart/db/altsyncram_g1p3.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}