prev_cmp_uart.tan.qmsg

Verilog编写的UART程序源代码。测试成功。支持字符串发送

{ "Info" "ITDB_TSU_RESULT" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[0\] rs232_rx clk 5.849 ns register " "Info: tsu for register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[0\]\" (data pin = \"rs232_rx\", clock pin = \"clk\") is 5.849 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.724 ns + Longest pin register " "Info: + Longest pin to register delay is 8.724 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns rs232_rx 1 PIN PIN_191 5 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_191; Fanout = 5; PIN Node = 'rs232_rx'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs232_rx } "NODE_NAME" } } { "my_uart_top.v" "" { Text "D:/mydesign/uart/my_uart_top.v" 7 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.313 ns) + CELL(0.319 ns) 8.616 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[0\]~feeder 2 COMB LCCOMB_X26_Y11_N4 1 " "Info: 2: + IC(7.313 ns) + CELL(0.319 ns) = 8.616 ns; Loc. = LCCOMB_X26_Y11_N4; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[0\]~feeder'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.632 ns" { rs232_rx sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[0]~feeder } "NODE_NAME" } } { "../../altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "D:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 948 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.724 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[0\] 3 REG LCFF_X26_Y11_N5 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.724 ns; Loc. = LCFF_X26_Y11_N5; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[0\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[0]~feeder sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[0] } "NODE_NAME" } } { "../../altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "D:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 948 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.411 ns ( 16.17 % ) " "Info: Total cell delay = 1.411 ns ( 16.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.313 ns ( 83.83 % ) " "Info: Total interconnect delay = 7.313 ns ( 83.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.724 ns" { rs232_rx sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[0]~feeder sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.724 ns" { rs232_rx {} rs232_rx~combout {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[0]~feeder {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[0] {} } { 0.000ns 0.000ns 7.313ns 0.000ns } { 0.000ns 0.984ns 0.319ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "../../altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "D:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 948 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.835 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.835 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "my_uart_top.v" "" { Text "D:/mydesign/uart/my_uart_top.v" 5 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 190 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 190; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "my_uart_top.v" "" { Text "D:/mydesign/uart/my_uart_top.v" 5 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.666 ns) 2.835 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[0\] 3 REG LCFF_X26_Y11_N5 1 " "Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.835 ns; Loc. = LCFF_X26_Y11_N5; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[0\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.556 ns" { clk~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[0] } "NODE_NAME" } } { "../../altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "D:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 948 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.70 % ) " "Info: Total cell delay = 1.806 ns ( 63.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.029 ns ( 36.30 % ) " "Info: Total interconnect delay = 1.029 ns ( 36.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.835 ns" { clk clk~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.835 ns" { clk {} clk~combout {} clk~clkctrl {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[0] {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.724 ns" { rs232_rx sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[0]~feeder sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.724 ns" { rs232_rx {} rs232_rx~combout {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[0]~feeder {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[0] {} } { 0.000ns 0.000ns 7.313ns 0.000ns } { 0.000ns 0.984ns 0.319ns 0.108ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.835 ns" { clk clk~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.835 ns" { clk {} clk~combout {} clk~clkctrl {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[0] {} } { 0.000ns 0.000ns 0.139ns 0.890ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk rs232_tx my_uart_tx:my_uart_tx\|rs232_tx_r 8.657 ns register " "Info: tco from clock \"clk\" to destination pin \"rs232_tx\" through register \"my_uart_tx:my_uart_tx\|rs232_tx_r\" is 8.657 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.852 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.852 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "my_uart_top.v" "" { Text "D:/mydesign/uart/my_uart_top.v" 5 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 190 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 190; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "my_uart_top.v" "" { Text "D:/mydesign/uart/my_uart_top.v" 5 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.907 ns) + CELL(0.666 ns) 2.852 ns my_uart_tx:my_uart_tx\|rs232_tx_r 3 REG LCFF_X16_Y8_N1 3 " "Info: 3: + IC(0.907 ns) + CELL(0.666 ns) = 2.852 ns; Loc. = LCFF_X16_Y8_N1; Fanout = 3; REG Node = 'my_uart_tx:my_uart_tx\|rs232_tx_r'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { clk~clkctrl my_uart_tx:my_uart_tx|rs232_tx_r } "NODE_NAME" } } { "my_uart_tx.v" "" { Text "D:/mydesign/uart/my_uart_tx.v" 74 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.32 % ) " "Info: Total cell delay = 1.806 ns ( 63.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.046 ns ( 36.68 % ) " "Info: Total interconnect delay = 1.046 ns ( 36.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.852 ns" { clk clk~clkctrl my_uart_tx:my_uart_tx|rs232_tx_r } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.852 ns" { clk {} clk~combout {} clk~clkctrl {} my_uart_tx:my_uart_tx|rs232_tx_r {} } { 0.000ns 0.000ns 0.139ns 0.907ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "my_uart_tx.v" "" { Text "D:/mydesign/uart/my_uart_tx.v" 74 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.501 ns + Longest register pin " "Info: + Longest register to pin delay is 5.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns my_uart_tx:my_uart_tx\|rs232_tx_r 1 REG LCFF_X16_Y8_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X16_Y8_N1; Fanout = 3; REG Node = 'my_uart_tx:my_uart_tx\|rs232_tx_r'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { my_uart_tx:my_uart_tx|rs232_tx_r } "NODE_NAME" } } { "my_uart_tx.v" "" { Text "D:/mydesign/uart/my_uart_tx.v" 74 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.245 ns) + CELL(3.256 ns) 5.501 ns rs232_tx 2 PIN PIN_182 0 " "Info: 2: + IC(2.245 ns) + CELL(3.256 ns) = 5.501 ns; Loc. = PIN_182; Fanout = 0; PIN Node = 'rs232_tx'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.501 ns" { my_uart_tx:my_uart_tx|rs232_tx_r rs232_tx } "NODE_NAME" } } { "my_uart_top.v" "" { Text "D:/mydesign/uart/my_uart_top.v" 8 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.256 ns ( 59.19 % ) " "Info: Total cell delay = 3.256 ns ( 59.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.245 ns ( 40.81 % ) " "Info: Total interconnect delay = 2.245 ns ( 40.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.501 ns" { my_uart_tx:my_uart_tx|rs232_tx_r rs232_tx } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.501 ns" { my_uart_tx:my_uart_tx|rs232_tx_r {} rs232_tx {} } { 0.000ns 2.245ns } { 0.000ns 3.256ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.852 ns" { clk clk~clkctrl my_uart_tx:my_uart_tx|rs232_tx_r } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.852 ns" { clk {} clk~combout {} clk~clkctrl {} my_uart_tx:my_uart_tx|rs232_tx_r {} } { 0.000ns 0.000ns 0.139ns 0.907ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.501 ns" { my_uart_tx:my_uart_tx|rs232_tx_r rs232_tx } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.501 ns" { my_uart_tx:my_uart_tx|rs232_tx_r {} rs232_tx {} } { 0.000ns 2.245ns } { 0.000ns 3.256ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}