uart.fit.summary

Verilog编写的UART程序源代码。测试成功。支持字符串发送

Fitter Status : Successful - Sun Apr 05 21:29:06 2009
Quartus II Version : 8.0 Build 215 05/29/2008 SJ Web Edition
Revision Name : uart
Top-level Entity Name : my_uart_top
Family : Cyclone II
Device : EP2C8Q208C8
Timing Models : Final
Total logic elements : 498 / 8,256 ( 6 % )
    Total combinational functions : 362 / 8,256 ( 4 % )
    Dedicated logic registers : 376 / 8,256 ( 5 % )
Total registers : 376
Total pins : 8 / 138 ( 6 % )
Total virtual pins : 3
Total memory bits : 384 / 165,888 ( < 1 % )
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )