uart.map.rpt

Verilog编写的UART程序源代码。测试成功。支持字符串发送

+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |my_uart_top|my_uart_tx:my_uart_tx|num[3] ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |my_uart_top|my_uart_rx:my_uart_rx|num[3] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------+


+-------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                  ;
+--------------------------------------------+----------------------------------------+
; Register name                              ; Reason for Removal                     ;
+--------------------------------------------+----------------------------------------+
; my_uart_tx:my_uart_tx|bps_start_r          ; Stuck at VCC due to stuck port data_in ;
; my_uart_rx:my_uart_rx|bps_start_r          ; Stuck at VCC due to stuck port data_in ;
; speed_select:speed_select|bps_para[12]     ; Stuck at VCC due to stuck port data_in ;
; speed_select:speed_select|bps_para[11]     ; Stuck at GND due to stuck port data_in ;
; speed_select:speed_select|bps_para[10]     ; Stuck at VCC due to stuck port data_in ;
; speed_select:speed_select|bps_para[7..9]   ; Stuck at GND due to stuck port data_in ;
; speed_select:speed_select|bps_para[6]      ; Stuck at VCC due to stuck port data_in ;
; speed_select:speed_select|bps_para[5]      ; Stuck at GND due to stuck port data_in ;
; speed_select:speed_select|bps_para[4]      ; Stuck at VCC due to stuck port data_in ;
; speed_select:speed_select|bps_para[3]      ; Stuck at GND due to stuck port data_in ;
; speed_select:speed_select|bps_para[0..2]   ; Stuck at VCC due to stuck port data_in ;
; speed_select:speed_select|bps_para_2[12]   ; Stuck at GND due to stuck port data_in ;
; speed_select:speed_select|bps_para_2[11]   ; Stuck at VCC due to stuck port data_in ;
; speed_select:speed_select|bps_para_2[10]   ; Stuck at GND due to stuck port data_in ;
; speed_select:speed_select|bps_para_2[9]    ; Stuck at VCC due to stuck port data_in ;
; speed_select:speed_select|bps_para_2[6..8] ; Stuck at GND due to stuck port data_in ;
; speed_select:speed_select|bps_para_2[5]    ; Stuck at VCC due to stuck port data_in ;
; speed_select:speed_select|bps_para_2[4]    ; Stuck at GND due to stuck port data_in ;
; speed_select:speed_select|bps_para_2[3]    ; Stuck at VCC due to stuck port data_in ;
; speed_select:speed_select|bps_para_2[2]    ; Stuck at GND due to stuck port data_in ;
; speed_select:speed_select|bps_para_2[0..1] ; Stuck at VCC due to stuck port data_in ;
; my_uart_rx:my_uart_rx|bps_start_r~en       ; Lost fanout                            ;
; my_uart_tx:my_uart_tx|bps_start_r~en       ; Lost fanout                            ;
; Total Number of Removed Registers = 30     ;                                        ;
+--------------------------------------------+----------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                                ;
+-----------------------------------+---------------------------+----------------------------------------------------------------------------+
; Register name                     ; Reason for Removal        ; Registers Removed due to This Register                                     ;
+-----------------------------------+---------------------------+----------------------------------------------------------------------------+
; my_uart_tx:my_uart_tx|bps_start_r ; Stuck at VCC              ; my_uart_rx:my_uart_rx|bps_start_r~en, my_uart_tx:my_uart_tx|bps_start_r~en ;
;                                   ; due to stuck port data_in ;                                                                            ;
+-----------------------------------+---------------------------+----------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Partition for Top-Level Resource Utilization by Entity                                                                                                                                             ;
+--------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------+--------------+
; Compilation Hierarchy Node     ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                    ; Library Name ;
+--------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------+--------------+
; |my_uart_top                   ; 63 (3)            ; 56 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |my_uart_top                           ; work         ;
;    |my_uart_rx:my_uart_rx|     ; 19 (19)           ; 25 (25)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |my_uart_top|my_uart_rx:my_uart_rx     ; work         ;
;    |my_uart_tx:my_uart_tx|     ; 20 (20)           ; 17 (17)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |my_uart_top|my_uart_tx:my_uart_tx     ; work         ;
;    |speed_select:speed_select| ; 21 (21)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |my_uart_top|speed_select:speed_select ; work         ;
+--------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |my_uart_top|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[5]      ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |my_uart_top|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|word_counter[2]                      ;
; 12:1               ; 4 bits    ; 32 LEs        ; 28 LEs               ; 4 LEs                  ; Yes        ; |my_uart_top|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[0]                           ;
; 3:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; No         ; |my_uart_top|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~10 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                                                                            ;
+---------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                   ; Reason for Removal                                                                                                                          ;
+---------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------+
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|buffer_write_enable_delayed                                ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|segment_shift_clk_ena                                      ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[0] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[0] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[1] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[1] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[2] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[2] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[3] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[3] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[4] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[4] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[5] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[5] ;
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count[6] ; Merged with sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[6] ;
; Total Number of Removed Registers = 8                                                                                           ;                                                                                                                                             ;
+---------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Partition "sld_signaltap:auto_signaltap_0" Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                                                                           ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                                                                                                                       ; Library Name ;
+------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |my_uart_top                                                                                         ; 200 (0)           ; 241 (0)      ; 384         ; 0            ; 0       ; 0         ; 0    ; 0            ; |my_uart_top                                                                                                                                                                                                                                                                                              ; work         ;
;    |sld_signaltap:auto_signaltap_0|                                                                  ; 200 (1)           ; 241 (0)      ; 384         ; 0            ; 0       ; 0         ; 0    ; 0            ; |my_uart_top|sld_signaltap:auto_signaltap_0                                                                                                                                                                                                                                                               ; work         ;
;       |sld_signaltap_impl:sld_signaltap_body|                                                        ; 199 (19)          ; 241 (41)     ; 384         ; 0            ; 0       ; 0         ; 0    ; 0            ; |my_uart_top|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body                                                                                                                                                                                                                         ; work         ;
;          |altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|                            ; 17 (0)            ; 46 (46)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |my_uart_top|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem                                                                                                                                                          ; work         ;
;             |lpm_decode:wdecoder|                                                                    ; 2 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |my_uart_top|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder                                                                                                                                      ; work         ;
;                |decode_rqf:auto_generated|                                                           ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |my_uart_top|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_rqf:auto_generated                                                                                                            ; work         ;
;             |lpm_mux:mux|                                                                            ; 15 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |my_uart_top|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm