uart.fit.rpt

Verilog编写的UART程序源代码。测试成功。支持字符串发送

; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                        ; Off                            ; Off                            ;
; PowerPlay Power Optimization                                       ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers                                              ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                  ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                        ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
; Maximum number of global clocks allowed                            ; -1                             ; -1                             ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Partition Preservation Settings                                                                                                                ;
+--------------------------------+-------------------+---------+------------------------------+------------------------+--------------------------------+
; Name                           ; # Preserved Nodes ; # Nodes ; Preservation Level Requested ; Netlist Type Used      ; Hierarchy                      ;
+--------------------------------+-------------------+---------+------------------------------+------------------------+--------------------------------+
; Top                            ; 0                 ; 131     ; Placement and Routing        ; Post-Synthesis Netlist ;                                ;
; sld_hub:sld_hub_inst           ; 0                 ; 176     ; Placement and Routing        ; Post-Synthesis Netlist ; sld_hub:sld_hub_inst           ;
; sld_signaltap:auto_signaltap_0 ; 0                 ; 444     ; Placement and Routing        ; Post-Synthesis Netlist ; sld_signaltap:auto_signaltap_0 ;
+--------------------------------+-------------------+---------+------------------------------+------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/mydesign/uart/uart.pin.


+-----------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                                         ;
+---------------------------------------------+-------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                   ;
+---------------------------------------------+-------------------------------------------------------------------------+
; Total logic elements                        ; 498 / 8,256 ( 6 % )                                                     ;
;     -- Combinational with no register       ; 122                                                                     ;
;     -- Register only                        ; 136                                                                     ;
;     -- Combinational with a register        ; 240                                                                     ;
;                                             ;                                                                         ;
; Logic element usage by number of LUT inputs ;                                                                         ;
;     -- 4 input functions                    ; 138                                                                     ;
;     -- 3 input functions                    ; 97                                                                      ;
;     -- <=2 input functions                  ; 127                                                                     ;
;     -- Register only                        ; 136                                                                     ;
;                                             ;                                                                         ;
; Logic elements by mode                      ;                                                                         ;
;     -- normal mode                          ; 314                                                                     ;
;     -- arithmetic mode                      ; 48                                                                      ;
;                                             ;                                                                         ;
; Total registers*                            ; 376 / 8,646 ( 4 % )                                                     ;
;     -- Dedicated logic registers            ; 376 / 8,256 ( 5 % )                                                     ;
;     -- I/O registers                        ; 0 / 390 ( 0 % )                                                         ;
;                                             ;                                                                         ;
; Total LABs:  partially or completely used   ; 45 / 516 ( 9 % )                                                        ;
; User inserted logic elements                ; 0                                                                       ;
; Virtual pins                                ; 3                                                                       ;
; I/O pins                                    ; 8 / 138 ( 6 % )                                                         ;
;     -- Clock pins                           ; 1 / 4 ( 25 % )                                                          ;
; Global signals                              ; 6                                                                       ;
; M4Ks                                        ; 1 / 36 ( 3 % )                                                          ;
; Total memory bits                           ; 384 / 165,888 ( < 1 % )                                                 ;
; Total RAM block bits                        ; 4,608 / 165,888 ( 3 % )                                                 ;
; Embedded Multiplier 9-bit elements          ; 0 / 36 ( 0 % )                                                          ;
; PLLs                                        ; 0 / 2 ( 0 % )                                                           ;
; Global clocks                               ; 6 / 8 ( 75 % )                                                          ;
; JTAGs                                       ; 1 / 1 ( 100 % )                                                         ;
; Average interconnect usage (total/H/V)      ; 1% / 1% / 0%                                                            ;
; Peak interconnect usage (total/H/V)         ; 3% / 4% / 2%                                                            ;
; Maximum fan-out node                        ; altera_internal_jtag~TCKUTAPclkctrl                                     ;
; Maximum fan-out                             ; 200                                                                     ;
; Highest non-global fan-out signal           ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] ;
; Highest non-global fan-out                  ; 34                                                                      ;
; Total fan-out                               ; 2438                                                                    ;
; Average fan-out                             ; 2.87                                                                    ;
+---------------------------------------------+-------------------------------------------------------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.