uart.map.summary

Verilog编写的UART程序源代码。测试成功。支持字符串发送

Analysis & Synthesis Status : Successful - Sun Apr 05 21:28:49 2009
Quartus II Version : 8.0 Build 215 05/29/2008 SJ Web Edition
Revision Name : uart
Top-level Entity Name : my_uart_top
Family : Cyclone II
Total logic elements : 63
    Total combinational functions : 63
    Dedicated logic registers : 56
Total registers : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total memory bits : N/A until Partition Merge
Embedded Multiplier 9-bit elements : N/A until Partition Merge
Total PLLs : N/A until Partition Merge