andarith.vhd

来自「用VHDL语言仿真乘法器设计。能够实现一般乘法运算。」· VHDL 代码 · 共 17 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity andarith is
port(abin:in std_logic;
	din:in std_logic_vector(7 downto 0);
	dout:out std_logic_vector(7 downto 0));
end andarith;
architecture behav of andarith is
begin
	process(abin,din)
	begin
	if abin='1' then dout<=din;
	else dout<="00000000";
	end if;
	end process;
end architecture behav;