adder8b.vhd

来自「用VHDL语言仿真乘法器设计。能够实现一般乘法运算。」· VHDL 代码 · 共 14 行

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity adder8b is
port(a,b:in std_logic_vector(7 downto 0);
	s:out std_logic_vector(8 downto 0));
end adder8b;
architecture behav of adder8b is
signal aa,bb:std_logic_vector(8 downto 0);
begin
		aa<='0'&a;
		bb<='0'&b;
		s<=aa+bb;
end architecture behav;