arictl.vhd

来自「用VHDL语言仿真乘法器设计。能够实现一般乘法运算。」· VHDL 代码 · 共 21 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity arictl is
port(clk,start:in std_logic;
	clkout,rstall,ariend:out std_logic);
end arictl;
architecture behav of arictl is
signal cnt4b:std_logic_vector(3 downto 0);
begin
rstall<=start;
process(clk,start)
begin
if start='1' then cnt4b<="0000";clkout<=clk;ariend<='0';
elsif clk'event and clk='1' then
	if cnt4b<7 then cnt4b<=cnt4b+1;clkout<=clk;ariend<='0';
	else clkout<='0';ariend<='1';
	end if;
end if;
end process;
end behav;