reg16b.vhd

来自「用VHDL语言仿真乘法器设计。能够实现一般乘法运算。」· VHDL 代码 · 共 20 行

library ieee;
use ieee.std_logic_1164.all;
entity reg16b is
port(clk,clr:in std_logic;
	d:in std_logic_vector(8 downto 0);
	q:out std_logic_vector(15 downto 0));
end reg16b;
architecture behav of reg16b is
signal r16s:std_logic_vector(15 downto 0);
begin
process(clk,clr)
begin
if clr='1' then r16s<="0000000000000000";
elsif clk'event and clk='1' then 
	r16s(6 downto 0)<=r16s(7 downto 1);
	r16s(15 downto 7)<=d;
end if;
end process;
q<=r16s;
end behav;