sreg8b.tan.summary

用VHDL语言仿真乘法器设计。能够实现一般乘法运算。

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 1.186 ns
From           : b[5]
To             : reg16b:inst3|r16s[15]
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 10.210 ns
From           : reg16b:inst3|r16s[7]
To             : dout[7]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.699 ns
From           : start
To             : sreg8b:inst4|reg8[5]
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 337.72 MHz ( period = 2.961 ns )
From           : sreg8b:inst4|reg8[0]
To             : reg16b:inst3|r16s[15]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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