jianbo.tan.qmsg

运用CORDIC算法完成对矢量信号模值及相位信息的运算

{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK CORDIC_PHI\[8\] CORDIC_PHI\[8\]~reg0 8.822 ns register " "Info: tco from clock \"CLOCK\" to destination pin \"CORDIC_PHI\[8\]\" through register \"CORDIC_PHI\[8\]~reg0\" is 8.822 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK source 2.636 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK\" to source register is 2.636 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.959 ns) 0.959 ns CLOCK 1 CLK PIN_J2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_J2; Fanout = 1; CLK Node = 'CLOCK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK } "NODE_NAME" } } { "jianbo.vhd" "" { Text "E:/新电子资料/我的论文/仿真结果/jianbo/jianbo.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.218 ns) + CELL(0.000 ns) 1.177 ns CLOCK~clkctrl 2 COMB CLKCTRL_G3 886 " "Info: 2: + IC(0.218 ns) + CELL(0.000 ns) = 1.177 ns; Loc. = CLKCTRL_G3; Fanout = 886; COMB Node = 'CLOCK~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.218 ns" { CLOCK CLOCK~clkctrl } "NODE_NAME" } } { "jianbo.vhd" "" { Text "E:/新电子资料/我的论文/仿真结果/jianbo/jianbo.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.922 ns) + CELL(0.537 ns) 2.636 ns CORDIC_PHI\[8\]~reg0 3 REG LCFF_X24_Y12_N31 1 " "Info: 3: + IC(0.922 ns) + CELL(0.537 ns) = 2.636 ns; Loc. = LCFF_X24_Y12_N31; Fanout = 1; REG Node = 'CORDIC_PHI\[8\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.459 ns" { CLOCK~clkctrl CORDIC_PHI[8]~reg0 } "NODE_NAME" } } { "jianbo.vhd" "" { Text "E:/新电子资料/我的论文/仿真结果/jianbo/jianbo.vhd" 42 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.496 ns ( 56.75 % ) " "Info: Total cell delay = 1.496 ns ( 56.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.140 ns ( 43.25 % ) " "Info: Total interconnect delay = 1.140 ns ( 43.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.636 ns" { CLOCK CLOCK~clkctrl CORDIC_PHI[8]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.636 ns" { CLOCK {} CLOCK~combout {} CLOCK~clkctrl {} CORDIC_PHI[8]~reg0 {} } { 0.000ns 0.000ns 0.218ns 0.922ns } { 0.000ns 0.959ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "jianbo.vhd" "" { Text "E:/新电子资料/我的论文/仿真结果/jianbo/jianbo.vhd" 42 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.936 ns + Longest register pin " "Info: + Longest register to pin delay is 5.936 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CORDIC_PHI\[8\]~reg0 1 REG LCFF_X24_Y12_N31 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y12_N31; Fanout = 1; REG Node = 'CORDIC_PHI\[8\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CORDIC_PHI[8]~reg0 } "NODE_NAME" } } { "jianbo.vhd" "" { Text "E:/新电子资料/我的论文/仿真结果/jianbo/jianbo.vhd" 42 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.168 ns) + CELL(2.768 ns) 5.936 ns CORDIC_PHI\[8\] 2 PIN PIN_B10 0 " "Info: 2: + IC(3.168 ns) + CELL(2.768 ns) = 5.936 ns; Loc. = PIN_B10; Fanout = 0; PIN Node = 'CORDIC_PHI\[8\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.936 ns" { CORDIC_PHI[8]~reg0 CORDIC_PHI[8] } "NODE_NAME" } } { "jianbo.vhd" "" { Text "E:/新电子资料/我的论文/仿真结果/jianbo/jianbo.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.768 ns ( 46.63 % ) " "Info: Total cell delay = 2.768 ns ( 46.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.168 ns ( 53.37 % ) " "Info: Total interconnect delay = 3.168 ns ( 53.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.936 ns" { CORDIC_PHI[8]~reg0 CORDIC_PHI[8] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.936 ns" { CORDIC_PHI[8]~reg0 {} CORDIC_PHI[8] {} } { 0.000ns 3.168ns } { 0.000ns 2.768ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.636 ns" { CLOCK CLOCK~clkctrl CORDIC_PHI[8]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.636 ns" { CLOCK {} CLOCK~combout {} CLOCK~clkctrl {} CORDIC_PHI[8]~reg0 {} } { 0.000ns 0.000ns 0.218ns 0.922ns } { 0.000ns 0.959ns 0.000ns 0.537ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.936 ns" { CORDIC_PHI[8]~reg0 CORDIC_PHI[8] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.936 ns" { CORDIC_PHI[8]~reg0 {} CORDIC_PHI[8] {} } { 0.000ns 3.168ns } { 0.000ns 2.768ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "Y0\[6\] RESET CLOCK 0.333 ns register " "Info: th for register \"Y0\[6\]\" (data pin = \"RESET\", clock pin = \"CLOCK\") is 0.333 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK destination 2.645 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK\" to destination register is 2.645 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.959 ns) 0.959 ns CLOCK 1 CLK PIN_J2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.959 ns) = 0.959 ns; Loc. = PIN_J2; Fanout = 1; CLK Node = 'CLOCK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK } "NODE_NAME" } } { "jianbo.vhd" "" { Text "E:/新电子资料/我的论文/仿真结果/jianbo/jianbo.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.218 ns) + CELL(0.000 ns) 1.177 ns CLOCK~clkctrl 2 COMB CLKCTRL_G3 886 " "Info: 2: + IC(0.218 ns) + CELL(0.000 ns) = 1.177 ns; Loc. = CLKCTRL_G3; Fanout = 886; COMB Node = 'CLOCK~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.218 ns" { CLOCK CLOCK~clkctrl } "NODE_NAME" } } { "jianbo.vhd" "" { Text "E:/新电子资料/我的论文/仿真结果/jianbo/jianbo.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.537 ns) 2.645 ns Y0\[6\] 3 REG LCFF_X14_Y13_N29 3 " "Info: 3: + IC(0.931 ns) + CELL(0.537 ns) = 2.645 ns; Loc. = LCFF_X14_Y13_N29; Fanout = 3; REG Node = 'Y0\[6\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.468 ns" { CLOCK~clkctrl Y0[6] } "NODE_NAME" } } { "jianbo.vhd" "" { Text "E:/新电子资料/我的论文/仿真结果/jianbo/jianbo.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.496 ns ( 56.56 % ) " "Info: Total cell delay = 1.496 ns ( 56.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.149 ns ( 43.44 % ) " "Info: Total interconnect delay = 1.149 ns ( 43.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.645 ns" { CLOCK CLOCK~clkctrl Y0[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.645 ns" { CLOCK {} CLOCK~combout {} CLOCK~clkctrl {} Y0[6] {} } { 0.000ns 0.000ns 0.218ns 0.931ns } { 0.000ns 0.959ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "jianbo.vhd" "" { Text "E:/新电子资料/我的论文/仿真结果/jianbo/jianbo.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.578 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.578 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.969 ns) 0.969 ns RESET 1 PIN PIN_J1 833 " "Info: 1: + IC(0.000 ns) + CELL(0.969 ns) = 0.969 ns; Loc. = PIN_J1; Fanout = 833; PIN Node = 'RESET'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { RESET } "NODE_NAME" } } { "jianbo.vhd" "" { Text "E:/新电子资料/我的论文/仿真结果/jianbo/jianbo.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.949 ns) + CELL(0.660 ns) 2.578 ns Y0\[6\] 2 REG LCFF_X14_Y13_N29 3 " "Info: 2: + IC(0.949 ns) + CELL(0.660 ns) = 2.578 ns; Loc. = LCFF_X14_Y13_N29; Fanout = 3; REG Node = 'Y0\[6\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.609 ns" { RESET Y0[6] } "NODE_NAME" } } { "jianbo.vhd" "" { Text "E:/新电子资料/我的论文/仿真结果/jianbo/jianbo.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.629 ns ( 63.19 % ) " "Info: Total cell delay = 1.629 ns ( 63.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.949 ns ( 36.81 % ) " "Info: Total interconnect delay = 0.949 ns ( 36.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.578 ns" { RESET Y0[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.578 ns" { RESET {} RESET~combout {} Y0[6] {} } { 0.000ns 0.000ns 0.949ns } { 0.000ns 0.969ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.645 ns" { CLOCK CLOCK~clkctrl Y0[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.645 ns" { CLOCK {} CLOCK~combout {} CLOCK~clkctrl {} Y0[6] {} } { 0.000ns 0.000ns 0.218ns 0.931ns } { 0.000ns 0.959ns 0.000ns 0.537ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.578 ns" { RESET Y0[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.578 ns" { RESET {} RESET~combout {} Y0[6] {} } { 0.000ns 0.000ns 0.949ns } { 0.000ns 0.969ns 0.660ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "124 " "Info: Allocated 124 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 23 21:13:51 2009 " "Info: Processing ended: Thu Apr 23 21:13:51 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}