📄 jianbo.map.rpt
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+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------+--------------+
; |JIANBO ; 1238 (1205) ; 886 (886) ; 0 ; 0 ; 0 ; 0 ; 88 ; 0 ; |JIANBO ; work ;
; |lpm_add_sub:Add2| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |JIANBO|lpm_add_sub:Add2 ; work ;
; |add_sub_sjg:auto_generated| ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |JIANBO|lpm_add_sub:Add2|add_sub_sjg:auto_generated ; work ;
+------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------------------------------+
; Registers Removed During Synthesis ;
+----------------------------------------+--------------------+
; Register name ; Reason for Removal ;
+----------------------------------------+--------------------+
; Z0[16] ; Merged with Z0[17] ;
; Z0[0..14] ; Merged with Z0[15] ;
; X0[16] ; Merged with X0[17] ;
; Y0[16] ; Merged with Y0[17] ;
; Z1[1..14] ; Merged with Z1[15] ;
; Total Number of Removed Registers = 32 ; ;
+----------------------------------------+--------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 886 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 32 ;
; Number of registers using Asynchronous Clear ; 54 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 832 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |JIANBO|X0[17] ;
; 3:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; Yes ; |JIANBO|X0[2] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add2 ;
+------------------------+-------------+----------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+----------------------------+
; LPM_WIDTH ; 18 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; DEFAULT ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_sjg ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add2 ;
+------------------------+-------------+----------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+----------------------------+
; LPM_WIDTH ; 18 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; DEFAULT ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_sjg ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Thu Apr 23 21:12:16 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jianbo -c jianbo
Info: Found 2 design units, including 1 entities, in source file jianbo.vhd
Info: Found design unit 1: JIANBO-a
Info: Found entity 1: JIANBO
Info: Elaborating entity "jianbo" for the top level hierarchy
Info: Duplicate registers merged to single register
Info: Duplicate register "Z0[16]" merged to single register "Z0[17]"
Info: Duplicate register "Z0[14]" merged to single register "Z0[15]"
Info: Duplicate register "Z0[13]" merged to single register "Z0[15]"
Info: Duplicate register "Z0[12]" merged to single register "Z0[15]"
Info: Duplicate register "Z0[11]" merged to single register "Z0[15]"
Info: Duplicate register "Z0[10]" merged to single register "Z0[15]"
Info: Duplicate register "Z0[9]" merged to single register "Z0[15]"
Info: Duplicate register "Z0[8]" merged to single register "Z0[15]"
Info: Duplicate register "Z0[7]" merged to single register "Z0[15]"
Info: Duplicate register "Z0[6]" merged to single register "Z0[15]"
Info: Duplicate register "Z0[5]" merged to single register "Z0[15]"
Info: Duplicate register "Z0[4]" merged to single register "Z0[15]"
Info: Duplicate register "Z0[3]" merged to single register "Z0[15]"
Info: Duplicate register "Z0[2]" merged to single register "Z0[15]"
Info: Duplicate register "Z0[1]" merged to single register "Z0[15]"
Info: Duplicate register "Z0[0]" merged to single register "Z0[15]"
Info: Duplicate registers merged to single register
Info: Duplicate register "X0[16]" merged to single register "X0[17]"
Info: Duplicate register "Y0[16]" merged to single register "Y0[17]"
Info: Duplicate register "Z1[1]" merged to single register "Z1[15]", power-up level changed
Info: Duplicate register "Z1[2]" merged to single register "Z1[15]", power-up level changed
Info: Duplicate register "Z1[3]" merged to single register "Z1[15]", power-up level changed
Info: Duplicate register "Z1[4]" merged to single register "Z1[15]", power-up level changed
Info: Duplicate register "Z1[5]" merged to single register "Z1[15]", power-up level changed
Info: Duplicate register "Z1[6]" merged to single register "Z1[15]", power-up level changed
Info: Duplicate register "Z1[7]" merged to single register "Z1[15]", power-up level changed
Info: Duplicate register "Z1[8]" merged to single register "Z1[15]", power-up level changed
Info: Duplicate register "Z1[9]" merged to single register "Z1[15]", power-up level changed
Info: Duplicate register "Z1[10]" merged to single register "Z1[15]", power-up level changed
Info: Duplicate register "Z1[11]" merged to single register "Z1[15]", power-up level changed
Info: Duplicate register "Z1[12]" merged to single register "Z1[15]", power-up level changed
Info: Duplicate register "Z1[13]" merged to single register "Z1[15]", power-up level changed
Info: Duplicate register "Z1[14]" merged to single register "Z1[15]", power-up level changed
Info: Inferred 2 megafunctions from design logic
Info: Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add2"
Info: Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add2"
Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Elaborated megafunction instantiation "lpm_add_sub:Add2"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_sjg.tdf
Info: Found entity 1: add_sub_sjg
Info: Implemented 1342 device resources after synthesis - the final resource count might be different
Info: Implemented 34 input pins
Info: Implemented 54 output pins
Info: Implemented 1254 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Allocated 166 megabytes of memory during processing
Info: Processing ended: Thu Apr 23 21:12:37 2009
Info: Elapsed time: 00:00:21
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