rom_nco.tan.rpt

来自「完整的基于ROM查找表的NCO 产生10位宽的正交信号」· RPT 代码 · 共 228 行 · 第 1/5 页

; Worst-case th                ; N/A   ; None          ; 0.594 ns                                       ; FREQW[20]                                                                                                     ; PHASE_PRO:b2v_PHASE_PRO|FREQW_REG[20]                                                ; --         ; ENA      ; 0            ;
; Clock Setup: 'CLOCK'         ; N/A   ; None          ; Restricted to 260.01 MHz ( period = 3.846 ns ) ; S_ROM:b2v_SROM|altsyncram:altsyncram_component|altsyncram_mt31:auto_generated|ram_block1a6~porta_address_reg9 ; S_ROM:b2v_SROM|altsyncram:altsyncram_component|altsyncram_mt31:auto_generated|q_a[9] ; CLOCK      ; CLOCK    ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                                                                                                               ;                                                                                      ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+------------+----------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP2C20F256C6       ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLOCK           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; ENA             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLOCK'                                                                                                                                                                                                                                                                                                                                                                                               ;