rom_nco.vhd.bak

完整的基于ROM查找表的NCO 产生10位宽的正交信号

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 7.2 Build 151 09/26/2007 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY ROM_NCO IS 
	port
	(
		CLOCK :  IN  STD_LOGIC;
		ENA :  IN  STD_LOGIC;
		RST :  IN  STD_LOGIC;
		FREQW :  IN  STD_LOGIC_VECTOR(31 downto 0);
		COS :  OUT  STD_LOGIC_VECTOR(9 downto 0);
		SIN :  OUT  STD_LOGIC_VECTOR(9 downto 0)
	);
END ROM_NCO;

ARCHITECTURE bdf_type OF ROM_NCO IS 

component c_rom
	PORT(clock : IN STD_LOGIC;
		 address : IN STD_LOGIC_VECTOR(9 downto 0);
		 q : OUT STD_LOGIC_VECTOR(9 downto 0)
	);
end component;

component cs_out
	PORT(CLOCK : IN STD_LOGIC;
		 RST : IN STD_LOGIC;
		 C_LUT : IN STD_LOGIC_VECTOR(9 downto 0);
		 DD : IN STD_LOGIC_VECTOR(1 downto 0);
		 S_LUT : IN STD_LOGIC_VECTOR(9 downto 0);
		 COS : OUT STD_LOGIC_VECTOR(9 downto 0);
		 SIN : OUT STD_LOGIC_VECTOR(9 downto 0)
	);
end component;

component phase_pro
	PORT(CLOCK : IN STD_LOGIC;
		 ENA : IN STD_LOGIC;
		 RST : IN STD_LOGIC;
		 FREQW : IN STD_LOGIC_VECTOR(31 downto 0);
		 DD : OUT STD_LOGIC_VECTOR(1 downto 0);
		 SPHASE_OUT : OUT STD_LOGIC_VECTOR(9 downto 0)
	);
end component;

component s_rom
	PORT(clock : IN STD_LOGIC;
		 address : IN STD_LOGIC_VECTOR(9 downto 0);
		 q : OUT STD_LOGIC_VECTOR(9 downto 0)
	);
end component;

signal	SYNTHESIZED_WIRE_5 :  STD_LOGIC_VECTOR(9 downto 0);
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(9 downto 0);
signal	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(1 downto 0);
signal	SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(9 downto 0);


BEGIN 



b2v_C_ROM : c_rom
PORT MAP(clock => CLOCK,
		 address => SYNTHESIZED_WIRE_5,
		 q => SYNTHESIZED_WIRE_1);

b2v_CS_OUT : cs_out
PORT MAP(CLOCK => CLOCK,
		 RST => RST,
		 C_LUT => SYNTHESIZED_WIRE_1,
		 DD => SYNTHESIZED_WIRE_2,
		 S_LUT => SYNTHESIZED_WIRE_3,
		 COS => COS,
		 SIN => SIN);

b2v_PHASE_PRO : phase_pro
PORT MAP(CLOCK => CLOCK,
		 ENA => ENA,
		 RST => RST,
		 FREQW => FREQW,
		 DD => SYNTHESIZED_WIRE_2,
		 SPHASE_OUT => SYNTHESIZED_WIRE_5);

b2v_SROM : s_rom
PORT MAP(clock => CLOCK,
		 address => SYNTHESIZED_WIRE_5,
		 q => SYNTHESIZED_WIRE_3);

END;