phase_pro.vhd

完整的基于ROM查找表的NCO 产生10位宽的正交信号

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;


ENTITY PHASE_PRO IS

	PORT
	(	
		CLOCK           : IN STD_LOGIC;
		ENA             : IN STD_LOGIC;
		RST             : IN std_logic;				
		FREQW			: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
		SPHASE_OUT	    : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
		DD              : OUT STD_LOGIC_VECTOR(1  DOWNTO 0)
	);	
END PHASE_PRO;

ARCHITECTURE A OF PHASE_PRO IS

	
	SIGNAL FREQW_REG          :  STD_LOGIC_VECTOR(31 DOWNTO 0):=X"00000000";
	SIGNAL PHASE_REG	      :  STD_LOGIC_VECTOR(31 DOWNTO 0):=X"00000000";
	SIGNAL DD1                :  STD_LOGIC_VECTOR(1 DOWNTO 0):="00";
	SIGNAL  SPHASE_CUT         :  STD_LOGIC_VECTOR(9 DOWNTO 0);
	CONSTANT MAX_PHASE        :  STD_LOGIC_VECTOR(9 DOWNTO 0):=(OTHERS=>'1');
	

 BEGIN

PROCESS(ENA)
 BEGIN
   
   IF ENA'EVENT AND ENA = '1' THEN
    
       
         FREQW_REG<=FREQW;

       
    END IF;
     
END PROCESS;







PROCESS(CLOCK,RST)
 BEGIN
   
   IF RST = '1' THEN
    
       PHASE_REG <=(OTHERS =>'0');

    
    ELSIF CLOCK'EVENT AND CLOCK = '1' THEN
       
 
    
       PHASE_REG <=PHASE_REG + FREQW_REG;
       
   END IF;
   
END PROCESS;







PROCESS(CLOCK,RST)--FOR COS/SIN TABLE
 BEGIN
  IF RST = '1' THEN
    SPHASE_CUT<="0000000000";
    DD1      <="00";
  ELSIF CLOCK'EVENT AND CLOCK = '1' THEN
  
         DD1 <=PHASE_REG(PHASE_REG'high downto PHASE_REG'high-1);
     IF PHASE_REG(PHASE_REG'high -1)='0' THEN
         SPHASE_CUT<=PHASE_REG(PHASE_REG'high-2 downto PHASE_REG'high-11);
         
     ELSE
        SPHASE_CUT<=MAX_PHASE-PHASE_REG(PHASE_REG'high-2 downto PHASE_REG'high-11);
        
     END IF;
 END IF;
END PROCESS;





PROCESS(CLOCK)
BEGIN
  IF CLOCK'EVENT AND CLOCK = '1' THEN
    SPHASE_OUT<=SPHASE_CUT;
    DD<=DD1;
  END IF;
END PROCESS;
END A;