cs_out.vhd

来自「完整的基于ROM查找表的NCO 产生10位宽的正交信号」· VHDL 代码 · 共 96 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;


ENTITY CS_OUT IS

	PORT
	(	
		CLOCK           : IN STD_LOGIC;
		RST             : IN std_logic;				
		DD			    : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
		S_LUT	        : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
		C_LUT           : IN STD_LOGIC_VECTOR(9  DOWNTO 0);
		SIN	            : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
		COS             : OUT STD_LOGIC_VECTOR(9  DOWNTO 0)
	);	
END CS_OUT;

ARCHITECTURE A OF CS_OUT IS

	
	SIGNAL S_REG          :  STD_LOGIC_VECTOR(9 DOWNTO 0);
	SIGNAL C_REG	      :  STD_LOGIC_VECTOR(9 DOWNTO 0);
	SIGNAL DD1            :  STD_LOGIC_VECTOR(1 DOWNTO 0);
	SIGNAL  DD2           :  STD_LOGIC_VECTOR(1 DOWNTO 0);
	CONSTANT OUT_ZEROS    :  STD_LOGIC_VECTOR(9 DOWNTO 0):=(OTHERS=>'0');
	
 BEGIN

PROCESS(CLOCK)
 BEGIN 
  IF CLOCK'EVENT AND CLOCK = '1' THEN
   DD1 <=DD;
   END IF;
END PROCESS;

PROCESS(CLOCK)
 BEGIN 
  IF CLOCK'EVENT AND CLOCK = '1' THEN
   DD2 <=DD1;
   END IF;
END PROCESS;
   
   
PROCESS(CLOCK,RST)
 BEGIN
IF CLOCK'EVENT AND CLOCK = '1' THEN
   
   IF RST = '1' THEN
    
       COS <=(OTHERS =>'0');

    
    ELSIF CLOCK'EVENT AND CLOCK = '1' THEN
    
       IF DD2="00" OR DD2="11" THEN
        COS <=C_LUT;
       ELSE
        COS<=OUT_ZEROS -C_LUT;

       
      END IF;
   END IF;
END IF;
 
END PROCESS;




 PROCESS(CLOCK,RST)
 BEGIN
   
   IF RST = '1' THEN
    
       SIN <=(OTHERS =>'0');

    
    ELSIF CLOCK'EVENT AND CLOCK = '1' THEN
    
       IF DD2="01" OR DD2="00" THEN
        SIN <=S_LUT;
       ELSE
        SIN<=OUT_ZEROS -S_LUT;

       
      END IF;
   END IF;

END PROCESS;


END A;