adcint.map.qmsg

基于VHDL语言的A/D采样控制程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 11 20:49:00 2009 " "Info: Processing started: Sat Apr 11 20:49:00 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ADCINT -c ADCINT " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ADCINT -c ADCINT" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADCINT.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ADCINT.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADCINT-ONE " "Info: Found design unit 1: ADCINT-ONE" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 adcint " "Info: Found entity 1: adcint" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ADCINT " "Info: Elaborating entity \"ADCINT\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|adcint\|current_state 7 " "Info: State machine \"\|adcint\|current_state\" contains 7 states" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 12 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|adcint\|current_state " "Info: Selected Auto state machine encoding method for state machine \"\|adcint\|current_state\"" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 12 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|adcint\|current_state " "Info: Encoding result for state machine \"\|adcint\|current_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "7 " "Info: Completed encoding using 7 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st6 " "Info: Encoded state bit \"current_state.st6\"" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st5 " "Info: Encoded state bit \"current_state.st5\"" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st4 " "Info: Encoded state bit \"current_state.st4\"" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st3 " "Info: Encoded state bit \"current_state.st3\"" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st2 " "Info: Encoded state bit \"current_state.st2\"" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st1 " "Info: Encoded state bit \"current_state.st1\"" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st0 " "Info: Encoded state bit \"current_state.st0\"" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adcint\|current_state.st0 0000000 " "Info: State \"\|adcint\|current_state.st0\" uses code string \"0000000\"" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adcint\|current_state.st1 0000011 " "Info: State \"\|adcint\|current_state.st1\" uses code string \"0000011\"" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adcint\|current_state.st2 0000101 " "Info: State \"\|adcint\|current_state.st2\" uses code string \"0000101\"" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adcint\|current_state.st3 0001001 " "Info: State \"\|adcint\|current_state.st3\" uses code string \"0001001\"" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adcint\|current_state.st4 0010001 " "Info: State \"\|adcint\|current_state.st4\" uses code string \"0010001\"" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adcint\|current_state.st5 0100001 " "Info: State \"\|adcint\|current_state.st5\" uses code string \"0100001\"" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|adcint\|current_state.st6 1000001 " "Info: State \"\|adcint\|current_state.st6\" uses code string \"1000001\"" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 12 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "ADDA VCC " "Warning: Pin \"ADDA\" stuck at VCC" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "39 " "Info: Implemented 39 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "16 " "Info: Implemented 16 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 11 20:49:01 2009 " "Info: Processing ended: Sat Apr 11 20:49:01 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}