adcint.tan.qmsg

基于VHDL语言的A/D采样控制程序

{ "Info" "ITDB_TH_RESULT" "REGL\[1\] D\[1\] CLK 2.330 ns register " "Info: th for register \"REGL\[1\]\" (data pin = \"D\[1\]\", clock pin = \"CLK\") is 2.330 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 6.728 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 6.728 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 7 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'CLK'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(0.698 ns) 3.215 ns current_state.st6 2 REG LC_X1_Y17_N6 11 " "Info: 2: + IC(1.689 ns) + CELL(0.698 ns) = 3.215 ns; Loc. = LC_X1_Y17_N6; Fanout = 11; REG Node = 'current_state.st6'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.387 ns" { CLK current_state.st6 } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.971 ns) + CELL(0.542 ns) 6.728 ns REGL\[1\] 3 REG LC_X1_Y7_N0 1 " "Info: 3: + IC(2.971 ns) + CELL(0.542 ns) = 6.728 ns; Loc. = LC_X1_Y7_N0; Fanout = 1; REG Node = 'REGL\[1\]'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "3.513 ns" { current_state.st6 REGL[1] } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.068 ns ( 30.74 % ) " "Info: Total cell delay = 2.068 ns ( 30.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.660 ns ( 69.26 % ) " "Info: Total interconnect delay = 4.660 ns ( 69.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "6.728 ns" { CLK current_state.st6 REGL[1] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "6.728 ns" { CLK CLK~out0 current_state.st6 REGL[1] } { 0.000ns 0.000ns 1.689ns 2.971ns } { 0.000ns 0.828ns 0.698ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 52 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.498 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.498 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns D\[1\] 1 PIN PIN_R19 1 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_R19; Fanout = 1; PIN Node = 'D\[1\]'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { D[1] } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.179 ns) + CELL(0.085 ns) 4.498 ns REGL\[1\] 2 REG LC_X1_Y7_N0 1 " "Info: 2: + IC(3.179 ns) + CELL(0.085 ns) = 4.498 ns; Loc. = LC_X1_Y7_N0; Fanout = 1; REG Node = 'REGL\[1\]'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "3.264 ns" { D[1] REGL[1] } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.319 ns ( 29.32 % ) " "Info: Total cell delay = 1.319 ns ( 29.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.179 ns ( 70.68 % ) " "Info: Total interconnect delay = 3.179 ns ( 70.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "4.498 ns" { D[1] REGL[1] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "4.498 ns" { D[1] D[1]~out0 REGL[1] } { 0.000ns 0.000ns 3.179ns } { 0.000ns 1.234ns 0.085ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "6.728 ns" { CLK current_state.st6 REGL[1] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "6.728 ns" { CLK CLK~out0 current_state.st6 REGL[1] } { 0.000ns 0.000ns 1.689ns 2.971ns } { 0.000ns 0.828ns 0.698ns 0.542ns } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "4.498 ns" { D[1] REGL[1] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "4.498 ns" { D[1] D[1]~out0 REGL[1] } { 0.000ns 0.000ns 3.179ns } { 0.000ns 1.234ns 0.085ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 11 20:49:17 2009 " "Info: Processing ended: Sat Apr 11 20:49:17 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}