adcint.tan.qmsg

基于VHDL语言的A/D采样控制程序

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "current_state.st6 " "Info: Detected ripple clock \"current_state.st6\" as buffer" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } } { "d:/program files/quartus ii/win/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii/win/Assignment Editor.qase" 1 { { 0 "current_state.st6" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register current_state.st3 current_state.st3 422.12 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 422.12 MHz between source register \"current_state.st3\" and destination register \"current_state.st3\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.848 ns + Longest register register " "Info: + Longest register to register delay is 0.848 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.st3 1 REG LC_X1_Y17_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y17_N2; Fanout = 2; REG Node = 'current_state.st3'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { current_state.st3 } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.529 ns) + CELL(0.319 ns) 0.848 ns current_state.st3 2 REG LC_X1_Y17_N2 2 " "Info: 2: + IC(0.529 ns) + CELL(0.319 ns) = 0.848 ns; Loc. = LC_X1_Y17_N2; Fanout = 2; REG Node = 'current_state.st3'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "0.848 ns" { current_state.st3 current_state.st3 } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.319 ns ( 37.62 % ) " "Info: Total cell delay = 0.319 ns ( 37.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.529 ns ( 62.38 % ) " "Info: Total interconnect delay = 0.529 ns ( 62.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "0.848 ns" { current_state.st3 current_state.st3 } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "0.848 ns" { current_state.st3 current_state.st3 } { 0.000ns 0.529ns } { 0.000ns 0.319ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.059 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.059 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 7 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'CLK'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(0.542 ns) 3.059 ns current_state.st3 2 REG LC_X1_Y17_N2 2 " "Info: 2: + IC(1.689 ns) + CELL(0.542 ns) = 3.059 ns; Loc. = LC_X1_Y17_N2; Fanout = 2; REG Node = 'current_state.st3'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.231 ns" { CLK current_state.st3 } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.79 % ) " "Info: Total cell delay = 1.370 ns ( 44.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.689 ns ( 55.21 % ) " "Info: Total interconnect delay = 1.689 ns ( 55.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "3.059 ns" { CLK current_state.st3 } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "3.059 ns" { CLK CLK~out0 current_state.st3 } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.059 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.059 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 7 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'CLK'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(0.542 ns) 3.059 ns current_state.st3 2 REG LC_X1_Y17_N2 2 " "Info: 2: + IC(1.689 ns) + CELL(0.542 ns) = 3.059 ns; Loc. = LC_X1_Y17_N2; Fanout = 2; REG Node = 'current_state.st3'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.231 ns" { CLK current_state.st3 } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.79 % ) " "Info: Total cell delay = 1.370 ns ( 44.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.689 ns ( 55.21 % ) " "Info: Total interconnect delay = 1.689 ns ( 55.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "3.059 ns" { CLK current_state.st3 } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "3.059 ns" { CLK CLK~out0 current_state.st3 } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "3.059 ns" { CLK current_state.st3 } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "3.059 ns" { CLK CLK~out0 current_state.st3 } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "3.059 ns" { CLK current_state.st3 } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "3.059 ns" { CLK CLK~out0 current_state.st3 } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "0.848 ns" { current_state.st3 current_state.st3 } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "0.848 ns" { current_state.st3 current_state.st3 } { 0.000ns 0.529ns } { 0.000ns 0.319ns } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "3.059 ns" { CLK current_state.st3 } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "3.059 ns" { CLK CLK~out0 current_state.st3 } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "3.059 ns" { CLK current_state.st3 } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "3.059 ns" { CLK CLK~out0 current_state.st3 } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { current_state.st3 } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { current_state.st3 } {  } {  } } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "current_state.st5 EOC CLK 1.791 ns register " "Info: tsu for register \"current_state.st5\" (data pin = \"EOC\", clock pin = \"CLK\") is 1.791 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.840 ns + Longest pin register " "Info: + Longest pin to register delay is 4.840 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns EOC 1 PIN PIN_L22 3 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L22; Fanout = 3; PIN Node = 'EOC'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { EOC } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.657 ns) + CELL(0.458 ns) 4.840 ns current_state.st5 2 REG LC_X1_Y17_N3 2 " "Info: 2: + IC(3.657 ns) + CELL(0.458 ns) = 4.840 ns; Loc. = LC_X1_Y17_N3; Fanout = 2; REG Node = 'current_state.st5'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "4.115 ns" { EOC current_state.st5 } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.183 ns ( 24.44 % ) " "Info: Total cell delay = 1.183 ns ( 24.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.657 ns ( 75.56 % ) " "Info: Total interconnect delay = 3.657 ns ( 75.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "4.840 ns" { EOC current_state.st5 } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "4.840 ns" { EOC EOC~out0 current_state.st5 } { 0.000ns 0.000ns 3.657ns } { 0.000ns 0.725ns 0.458ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.059 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.059 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 7 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'CLK'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(0.542 ns) 3.059 ns current_state.st5 2 REG LC_X1_Y17_N3 2 " "Info: 2: + IC(1.689 ns) + CELL(0.542 ns) = 3.059 ns; Loc. = LC_X1_Y17_N3; Fanout = 2; REG Node = 'current_state.st5'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.231 ns" { CLK current_state.st5 } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.79 % ) " "Info: Total cell delay = 1.370 ns ( 44.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.689 ns ( 55.21 % ) " "Info: Total interconnect delay = 1.689 ns ( 55.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "3.059 ns" { CLK current_state.st5 } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "3.059 ns" { CLK CLK~out0 current_state.st5 } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "4.840 ns" { EOC current_state.st5 } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "4.840 ns" { EOC EOC~out0 current_state.st5 } { 0.000ns 0.000ns 3.657ns } { 0.000ns 0.725ns 0.458ns } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "3.059 ns" { CLK current_state.st5 } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "3.059 ns" { CLK CLK~out0 current_state.st5 } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Q\[0\] REGL\[0\] 10.474 ns register " "Info: tco from clock \"CLK\" to destination pin \"Q\[0\]\" through register \"REGL\[0\]\" is 10.474 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 6.755 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 6.755 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 7 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'CLK'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(0.698 ns) 3.215 ns current_state.st6 2 REG LC_X1_Y17_N6 11 " "Info: 2: + IC(1.689 ns) + CELL(0.698 ns) = 3.215 ns; Loc. = LC_X1_Y17_N6; Fanout = 11; REG Node = 'current_state.st6'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "2.387 ns" { CLK current_state.st6 } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.998 ns) + CELL(0.542 ns) 6.755 ns REGL\[0\] 3 REG LC_X33_Y1_N2 1 " "Info: 3: + IC(2.998 ns) + CELL(0.542 ns) = 6.755 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'REGL\[0\]'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "3.540 ns" { current_state.st6 REGL[0] } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.068 ns ( 30.61 % ) " "Info: Total cell delay = 2.068 ns ( 30.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.687 ns ( 69.39 % ) " "Info: Total interconnect delay = 4.687 ns ( 69.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "6.755 ns" { CLK current_state.st6 REGL[0] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "6.755 ns" { CLK CLK~out0 current_state.st6 REGL[0] } { 0.000ns 0.000ns 1.689ns 2.998ns } { 0.000ns 0.828ns 0.698ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 52 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.563 ns + Longest register pin " "Info: + Longest register to pin delay is 3.563 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REGL\[0\] 1 REG LC_X33_Y1_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'REGL\[0\]'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "" { REGL[0] } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.159 ns) + CELL(2.404 ns) 3.563 ns Q\[0\] 2 PIN PIN_P9 0 " "Info: 2: + IC(1.159 ns) + CELL(2.404 ns) = 3.563 ns; Loc. = PIN_P9; Fanout = 0; PIN Node = 'Q\[0\]'" {  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "3.563 ns" { REGL[0] Q[0] } "NODE_NAME" } } { "ADCINT.vhd" "" { Text "E:/Quartus II/ADCINT/ADCINT.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 67.47 % ) " "Info: Total cell delay = 2.404 ns ( 67.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.159 ns ( 32.53 % ) " "Info: Total interconnect delay = 1.159 ns ( 32.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "3.563 ns" { REGL[0] Q[0] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "3.563 ns" { REGL[0] Q[0] } { 0.000ns 1.159ns } { 0.000ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "6.755 ns" { CLK current_state.st6 REGL[0] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "6.755 ns" { CLK CLK~out0 current_state.st6 REGL[0] } { 0.000ns 0.000ns 1.689ns 2.998ns } { 0.000ns 0.828ns 0.698ns 0.542ns } } } { "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii/win/TimingClosureFloorplan.fld" "" "3.563 ns" { REGL[0] Q[0] } "NODE_NAME" } } { "d:/program files/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus ii/win/Technology_Viewer.qrui" "3.563 ns" { REGL[0] Q[0] } { 0.000ns 1.159ns } { 0.000ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}