adcint.vhd

基于VHDL语言的A/D采样控制程序

---ADC0809的采样控制电路；  
library ieee;
use ieee.std_logic_1164.all;
entity adcint is
  port( D       :  in  std_logic_vector(7 downto 0);  ---ADC0809的8位转换数据  
        CLK,EOC :  in std_logic;
        LOCK1,ALE,START,OE,ADDA : OUT STD_LOGIC;      ---CLK是转换工作时钟  
        Q       :  OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ADCINT;
ARCHITECTURE ONE OF ADCINT IS
   TYPE  states  IS (st0,st1,st2,st3,st4,st5,st6);
   signal current_state,next_state : states:=st0;
   signal REGL   :  STD_LOGIC_VECTOR(7 DOWNTO 0);
   signal LOCK   :  STD_LOGIC;
BEGIN 
   ADDA<='1'; LOCK1<=LOCK;
PROCESS(current_state,EOC) 
BEGIN
  case current_state is
      when st0=>ALE<='0';START<='0';OE<='0';LOCK<='0';
                next_state<=st1;
      when st1=>ALE<='1';START<='0';OE<='0';LOCK<='0';
                next_state<=st2;
      when st2=>ALE<='0';START<='1';OE<='0';LOCK<='0';
                next_state<=st3;
      when st3=>ALE<='0';START<='0';OE<='0';LOCK<='0';
                if EOC='1' THEN next_state<=st3;
                else next_state<=st4;
                end if;
      when st4=>ALE<='0';START<='0';OE<='0';LOCK<='0';
                if EOC='0' THEN next_state<=st4;
                else next_state<=st5;
                end if;
      when st5=>ALE<='0';START<='0';OE<='1';LOCK<='0';
                next_state<=st6;
      when st6=>ALE<='0';START<='0';OE<='1';LOCK<='1';
                next_state<=st0;
      when others=>ALE<='0';START<='0';OE<='0';LOCK<='0';
                next_state<=st0;
   end case;
end process;

  process(clk)
    begin
     if(clk'event and clk='1') then
       current_state<=next_state;
     end if;
  end process;

 process(lock)
  begin
  if lock='1' and lock'event then
      regl<=D;
  end if;
 end process;
  Q<=REGL;
end one;