adcint.map.summary

基于VHDL语言的A/D采样控制程序

Analysis & Synthesis Status : Successful - Sat Apr 11 20:49:01 2009
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Web Edition
Revision Name : ADCINT
Top-level Entity Name : adcint
Family : Stratix
Total logic elements : 16
Total pins : 23
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0