adcint.tan.rpt

基于VHDL语言的A/D采样控制程序

+-------+--------------+------------+------+-------------------+----------+


+----------------------------------------------------------------------------+
; tco                                                                        ;
+-------+--------------+------------+-------------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From              ; To    ; From Clock ;
+-------+--------------+------------+-------------------+-------+------------+
; N/A   ; None         ; 10.474 ns  ; REGL[0]           ; Q[0]  ; CLK        ;
; N/A   ; None         ; 10.407 ns  ; REGL[2]           ; Q[2]  ; CLK        ;
; N/A   ; None         ; 10.092 ns  ; REGL[5]           ; Q[5]  ; CLK        ;
; N/A   ; None         ; 10.056 ns  ; REGL[1]           ; Q[1]  ; CLK        ;
; N/A   ; None         ; 10.046 ns  ; REGL[6]           ; Q[6]  ; CLK        ;
; N/A   ; None         ; 9.976 ns   ; REGL[3]           ; Q[3]  ; CLK        ;
; N/A   ; None         ; 9.950 ns   ; REGL[4]           ; Q[4]  ; CLK        ;
; N/A   ; None         ; 9.942 ns   ; REGL[7]           ; Q[7]  ; CLK        ;
; N/A   ; None         ; 7.547 ns   ; current_state.st5 ; OE    ; CLK        ;
; N/A   ; None         ; 7.494 ns   ; current_state.st6 ; LOCK1 ; CLK        ;
; N/A   ; None         ; 7.026 ns   ; current_state.st2 ; START ; CLK        ;
; N/A   ; None         ; 7.001 ns   ; current_state.st6 ; OE    ; CLK        ;
; N/A   ; None         ; 6.863 ns   ; current_state.st1 ; ALE   ; CLK        ;
+-------+--------------+------------+-------------------+-------+------------+


+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+-----------+------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                ; To Clock ;
+---------------+-------------+-----------+------+-------------------+----------+
; N/A           ; None        ; 2.330 ns  ; D[1] ; REGL[1]           ; CLK      ;
; N/A           ; None        ; 2.252 ns  ; D[3] ; REGL[3]           ; CLK      ;
; N/A           ; None        ; 2.227 ns  ; D[4] ; REGL[4]           ; CLK      ;
; N/A           ; None        ; 2.218 ns  ; D[7] ; REGL[7]           ; CLK      ;
; N/A           ; None        ; 2.189 ns  ; D[6] ; REGL[6]           ; CLK      ;
; N/A           ; None        ; 2.014 ns  ; D[0] ; REGL[0]           ; CLK      ;
; N/A           ; None        ; 1.929 ns  ; D[2] ; REGL[2]           ; CLK      ;
; N/A           ; None        ; 1.868 ns  ; D[5] ; REGL[5]           ; CLK      ;
; N/A           ; None        ; -1.674 ns ; EOC  ; current_state.st4 ; CLK      ;
; N/A           ; None        ; -1.681 ns ; EOC  ; current_state.st5 ; CLK      ;
; N/A           ; None        ; -1.681 ns ; EOC  ; current_state.st3 ; CLK      ;
+---------------+-------------+-----------+------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
    Info: Processing started: Sat Apr 11 20:49:17 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ADCINT -c ADCINT --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "current_state.st6" as buffer
Info: Clock "CLK" Internal fmax is restricted to 422.12 MHz between source register "current_state.st3" and destination register "current_state.st3"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.848 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y17_N2; Fanout = 2; REG Node = 'current_state.st3'
            Info: 2: + IC(0.529 ns) + CELL(0.319 ns) = 0.848 ns; Loc. = LC_X1_Y17_N2; Fanout = 2; REG Node = 'current_state.st3'
            Info: Total cell delay = 0.319 ns ( 37.62 % )
            Info: Total interconnect delay = 0.529 ns ( 62.38 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 3.059 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'CLK'
                Info: 2: + IC(1.689 ns) + CELL(0.542 ns) = 3.059 ns; Loc. = LC_X1_Y17_N2; Fanout = 2; REG Node = 'current_state.st3'
                Info: Total cell delay = 1.370 ns ( 44.79 % )
                Info: Total interconnect delay = 1.689 ns ( 55.21 % )
            Info: - Longest clock path from clock "CLK" to source register is 3.059 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'CLK'
                Info: 2: + IC(1.689 ns) + CELL(0.542 ns) = 3.059 ns; Loc. = LC_X1_Y17_N2; Fanout = 2; REG Node = 'current_state.st3'
                Info: Total cell delay = 1.370 ns ( 44.79 % )
                Info: Total interconnect delay = 1.689 ns ( 55.21 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "current_state.st5" (data pin = "EOC", clock pin = "CLK") is 1.791 ns
    Info: + Longest pin to register delay is 4.840 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L22; Fanout = 3; PIN Node = 'EOC'
        Info: 2: + IC(3.657 ns) + CELL(0.458 ns) = 4.840 ns; Loc. = LC_X1_Y17_N3; Fanout = 2; REG Node = 'current_state.st5'
        Info: Total cell delay = 1.183 ns ( 24.44 % )
        Info: Total interconnect delay = 3.657 ns ( 75.56 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 3.059 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'CLK'
        Info: 2: + IC(1.689 ns) + CELL(0.542 ns) = 3.059 ns; Loc. = LC_X1_Y17_N3; Fanout = 2; REG Node = 'current_state.st5'
        Info: Total cell delay = 1.370 ns ( 44.79 % )
        Info: Total interconnect delay = 1.689 ns ( 55.21 % )
Info: tco from clock "CLK" to destination pin "Q[0]" through register "REGL[0]" is 10.474 ns
    Info: + Longest clock path from clock "CLK" to source register is 6.755 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'CLK'
        Info: 2: + IC(1.689 ns) + CELL(0.698 ns) = 3.215 ns; Loc. = LC_X1_Y17_N6; Fanout = 11; REG Node = 'current_state.st6'
        Info: 3: + IC(2.998 ns) + CELL(0.542 ns) = 6.755 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'REGL[0]'
        Info: Total cell delay = 2.068 ns ( 30.61 % )
        Info: Total interconnect delay = 4.687 ns ( 69.39 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.563 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'REGL[0]'
        Info: 2: + IC(1.159 ns) + CELL(2.404 ns) = 3.563 ns; Loc. = PIN_P9; Fanout = 0; PIN Node = 'Q[0]'
        Info: Total cell delay = 2.404 ns ( 67.47 % )
        Info: Total interconnect delay = 1.159 ns ( 32.53 % )
Info: th for register "REGL[1]" (data pin = "D[1]", clock pin = "CLK") is 2.330 ns
    Info: + Longest clock path from clock "CLK" to destination register is 6.728 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'CLK'
        Info: 2: + IC(1.689 ns) + CELL(0.698 ns) = 3.215 ns; Loc. = LC_X1_Y17_N6; Fanout = 11; REG Node = 'current_state.st6'
        Info: 3: + IC(2.971 ns) + CELL(0.542 ns) = 6.728 ns; Loc. = LC_X1_Y7_N0; Fanout = 1; REG Node = 'REGL[1]'
        Info: Total cell delay = 2.068 ns ( 30.74 % )
        Info: Total interconnect delay = 4.660 ns ( 69.26 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 4.498 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_R19; Fanout = 1; PIN Node = 'D[1]'
        Info: 2: + IC(3.179 ns) + CELL(0.085 ns) = 4.498 ns; Loc. = LC_X1_Y7_N0; Fanout = 1; REG Node = 'REGL[1]'
        Info: Total cell delay = 1.319 ns ( 29.32 % )
        Info: Total interconnect delay = 3.179 ns ( 70.68 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Sat Apr 11 20:49:17 2009
    Info: Elapsed time: 00:00:00