uart_regs.fit.qmsg

ALTER FPGA/GPLD设计（初级篇）的源码

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.850 ns memory register " "Info: Estimated most critical path is memory to register delay of 4.850 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_3651:auto_generated\|a_dpfifo_ac51:dpfifo\|dpram_ea21:FIFOram\|altsyncram_gml1:altsyncram1\|ram_block2a7~portb_address_reg3 1 MEM M512_X26_Y23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X26_Y23; Fanout = 1; MEM Node = 'uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_3651:auto_generated\|a_dpfifo_ac51:dpfifo\|dpram_ea21:FIFOram\|altsyncram_gml1:altsyncram1\|ram_block2a7~portb_address_reg3'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|dpram_ea21:FIFOram|altsyncram_gml1:altsyncram1|ram_block2a7~portb_address_reg3 } "NODE_NAME" } } { "db/altsyncram_gml1.tdf" "" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/altsyncram_gml1.tdf" 258 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.066 ns) 3.066 ns uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_3651:auto_generated\|a_dpfifo_ac51:dpfifo\|dpram_ea21:FIFOram\|altsyncram_gml1:altsyncram1\|q_b\[7\] 2 MEM M512_X26_Y23 2 " "Info: 2: + IC(0.000 ns) + CELL(3.066 ns) = 3.066 ns; Loc. = M512_X26_Y23; Fanout = 2; MEM Node = 'uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_3651:auto_generated\|a_dpfifo_ac51:dpfifo\|dpram_ea21:FIFOram\|altsyncram_gml1:altsyncram1\|q_b\[7\]'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.066 ns" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|dpram_ea21:FIFOram|altsyncram_gml1:altsyncram1|ram_block2a7~portb_address_reg3 uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|dpram_ea21:FIFOram|altsyncram_gml1:altsyncram1|q_b[7] } "NODE_NAME" } } { "db/altsyncram_gml1.tdf" "" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/altsyncram_gml1.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.545 ns) + CELL(0.087 ns) 3.698 ns uart_transmitter:transmitter\|WideXor0~40 3 COMB LAB_X27_Y23 1 " "Info: 3: + IC(0.545 ns) + CELL(0.087 ns) = 3.698 ns; Loc. = LAB_X27_Y23; Fanout = 1; COMB Node = 'uart_transmitter:transmitter\|WideXor0~40'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "0.632 ns" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|dpram_ea21:FIFOram|altsyncram_gml1:altsyncram1|q_b[7] uart_transmitter:transmitter|WideXor0~40 } "NODE_NAME" } } { "../src/uart_transmitter.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_transmitter.v" 95 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.087 ns) 4.212 ns uart_transmitter:transmitter\|WideXor0 4 COMB LAB_X27_Y23 1 " "Info: 4: + IC(0.427 ns) + CELL(0.087 ns) = 4.212 ns; Loc. = LAB_X27_Y23; Fanout = 1; COMB Node = 'uart_transmitter:transmitter\|WideXor0'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "0.514 ns" { uart_transmitter:transmitter|WideXor0~40 uart_transmitter:transmitter|WideXor0 } "NODE_NAME" } } { "../src/uart_transmitter.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_transmitter.v" 95 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.055 ns) + CELL(0.583 ns) 4.850 ns uart_transmitter:transmitter\|parity_xor 5 REG LAB_X27_Y23 2 " "Info: 5: + IC(0.055 ns) + CELL(0.583 ns) = 4.850 ns; Loc. = LAB_X27_Y23; Fanout = 2; REG Node = 'uart_transmitter:transmitter\|parity_xor'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "0.638 ns" { uart_transmitter:transmitter|WideXor0 uart_transmitter:transmitter|parity_xor } "NODE_NAME" } } { "../src/uart_transmitter.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_transmitter.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.823 ns ( 78.82 % ) " "Info: Total cell delay = 3.823 ns ( 78.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.027 ns ( 21.18 % ) " "Info: Total interconnect delay = 1.027 ns ( 21.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "4.850 ns" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|dpram_ea21:FIFOram|altsyncram_gml1:altsyncram1|ram_block2a7~portb_address_reg3 uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|dpram_ea21:FIFOram|altsyncram_gml1:altsyncram1|q_b[7] uart_transmitter:transmitter|WideXor0~40 uart_transmitter:transmitter|WideXor0 uart_transmitter:transmitter|parity_xor } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 3 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 3%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x21_y21 x31_y31 " "Info: The peak interconnect region extends from location x21_y21 to location x31_y31" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "uart_receiver:receiver\|aclr " "Info: Node uart_receiver:receiver\|aclr uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo\|a_fefifo_66f:fifo_state\|b_full " "Info: Port clear -- assigned as a global for destination node uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo\|a_fefifo_66f:fifo_state\|b_full -- routed using non-global resources" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|a_fefifo_66f:fifo_state|b_full } "NODE_NAME" } } { "e:/quartusii6.0/win/Assignment Editor.qase" "" { Assignment "e:/quartusii6.0/win/Assignment Editor.qase" 1 { { 0 "uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo\|a_fefifo_66f:fifo_state\|b_full" } } } } { "db/a_fefifo_66f.tdf" "" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/a_fefifo_66f.tdf" 36 2 0 } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|a_fefifo_66f:fifo_state|b_full } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo\|a_fefifo_66f:fifo_state\|b_non_empty " "Info: Port clear -- assigned as a global for destination node uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo\|a_fefifo_66f:fifo_state\|b_non_empty -- routed using non-global resources" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|a_fefifo_66f:fifo_state|b_non_empty } "NODE_NAME" } } { "e:/quartusii6.0/win/Assignment Editor.qase" "" { Assignment "e:/quartusii6.0/win/Assignment Editor.qase" 1 { { 0 "uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo\|a_fefifo_66f:fifo_state\|b_non_empty" } } } } { "db/a_fefifo_66f.tdf" "" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/a_fefifo_66f.tdf" 37 2 0 } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|a_fefifo_66f:fifo_state|b_non_empty } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_receiver:receiver|aclr } "NODE_NAME" } } { "e:/quartusii6.0/win/Assignment Editor.qase" "" { Assignment "e:/quartusii6.0/win/Assignment Editor.qase" 1 { { 0 "uart_receiver:receiver\|aclr" } } } } { "../src/uart_receiver.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_receiver.v" 29 -1 0 } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_receiver:receiver|aclr } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "uart_transmitter:transmitter\|aclr " "Info: Node uart_transmitter:transmitter\|aclr uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_3651:auto_generated\|a_dpfifo_ac51:dpfifo\|a_fefifo_66f:fifo_state\|b_non_empty " "Info: Port clear -- assigned as a global for destination node uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_3651:auto_generated\|a_dpfifo_ac51:dpfifo\|a_fefifo_66f:fifo_state\|b_non_empty -- routed using non-global resources" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|a_fefifo_66f:fifo_state|b_non_empty } "NODE_NAME" } } { "e:/quartusii6.0/win/Assignment Editor.qase" "" { Assignment "e:/quartusii6.0/win/Assignment Editor.qase" 1 { { 0 "uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_3651:auto_generated\|a_dpfifo_ac51:dpfifo\|a_fefifo_66f:fifo_state\|b_non_empty" } } } } { "db/a_fefifo_66f.tdf" "" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/a_fefifo_66f.tdf" 37 2 0 } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|a_fefifo_66f:fifo_state|b_non_empty } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_3651:auto_generated\|a_dpfifo_ac51:dpfifo\|cntr_re8:rd_ptr_count\|counter_cella0 " "Info: Port clear -- assigned as a global for destination node uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_3651:auto_generated\|a_dpfifo_ac51:dpfifo\|cntr_re8:rd_ptr_count\|counter_cella0 -- routed using non-global resources" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|cntr_re8:rd_ptr_count|safe_q[0] } "NODE_NAME" } } { "e:/quartusii6.0/win/Assignment Editor.qase" "" { Assignment "e:/quartusii6.0/win/Assignment Editor.qase" 1 { { 0 "uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_3651:auto_generated\|a_dpfifo_ac51:dpfifo\|cntr_re8:rd_ptr_count\|safe_q\[0\]" } } } } { "db/cntr_re8.tdf" "" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/cntr_re8.tdf" 69 8 0 } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|cntr_re8:rd_ptr_count|safe_q[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_3651:auto_generated\|a_dpfifo_ac51:dpfifo\|cntr_re8:rd_ptr_count\|counter_cella1 " "Info: Port clear -- assigned as a global for destination node uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_3651:auto_generated\|a_dpfifo_ac51:dpfifo\|cntr_re8:rd_ptr_count\|counter_cella1 -- routed using non-global resources" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|cntr_re8:rd_ptr_count|safe_q[1] } "NODE_NAME" } } { "e:/quartusii6.0/win/Assignment Editor.qase" "" { Assignment "e:/quartusii6.0/win/Assignment Editor.qase" 1 { { 0 "uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_3651:auto_generated\|a_dpfifo_ac51:dpfifo\|cntr_re8:rd_ptr_count\|safe_q\[1\]" } } } } { "db/cntr_re8.tdf" "" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/cntr_re8.tdf" 69 8 0 } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|cntr_re8:rd_ptr_count|safe_q[1] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_3651:auto_generated\|a_dpfifo_ac51:dpfifo\|cntr_re8:rd_ptr_count\|counter_cella2 " "Info: Port clear -- assigned as a global for destination node uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_3651:auto_generated\|a_dpfifo_ac51:dpfifo\|cntr_re8:rd_ptr_count\|counter_cella2 -- routed using non-global resources" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|cntr_re8:rd_ptr_count|safe_q[2] } "NODE_NAME" } } { "e:/quartusii6.0/win/Assignment Editor.qase" "" { Assignment "e:/quartusii6.0/win/Assignment Editor.qase" 1 { { 0 "uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_3651:auto_generated\|a_dpfifo_ac51:dpfifo\|cntr_re8:rd_ptr_count\|safe_q\[2\]" } } } } { "db/cntr_re8.tdf" "" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/cntr_re8.tdf" 69 8 0 } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|cntr_re8:rd_ptr_count|safe_q[2] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_3651:auto_generated\|a_dpfifo_ac51:dpfifo\|cntr_re8:rd_ptr_count\|counter_cella3 " "Info: Port clear -- assigned as a global for destination node uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_3651:auto_generated\|a_dpfifo_ac51:dpfifo\|cntr_re8:rd_ptr_count\|counter_cella3 -- routed using non-global resources" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|cntr_re8:rd_ptr_count|safe_q[3] } "NODE_NAME" } } { "e:/quartusii6.0/win/Assignment Editor.qase" "" { Assignment "e:/quartusii6.0/win/Assignment Editor.qase" 1 { { 0 "uart_transmitter:transmitter\|myfifo_8:myfifo_u1\|scfifo:scfifo_component\|scfifo_3651:auto_generated\|a_dpfifo_ac51:dpfifo\|cntr_re8:rd_ptr_count\|safe_q\[3\]" } } } } { "db/cntr_re8.tdf" "" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/cntr_re8.tdf" 69 8 0 } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|cntr_re8:rd_ptr_count|safe_q[3] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_transmitter:transmitter|aclr } "NODE_NAME" } } { "e:/quartusii6.0/win/Assignment Editor.qase" "" { Assignment "e:/quartusii6.0/win/Assignment Editor.qase" 1 { { 0 "uart_transmitter:transmitter\|aclr" } } } } { "../src/uart_transmitter.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_transmitter.v" 42 -1 0 } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_transmitter:transmitter|aclr } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 08 10:30:48 2008 " "Info: Processing ended: Sat Nov 08 10:30:48 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/Example/Example-b3-1/uart_regs/dev/uart_regs.fit.smsg " "Info: Generated suppressed messages file D:/Example/Example-b3-1/uart_regs/dev/uart_regs.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}