uart_regs.sim.qmsg

ALTER FPGA/GPLD设计（初级篇）的源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 08 10:37:29 2008 " "Info: Processing started: Sat Nov 08 10:37:29 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off uart_regs -c uart_regs " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off uart_regs -c uart_regs" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "tf_push " "Warning: Ignored node in vector source file. Can't find corresponding node name \"tf_push\" in design." {  } { { "D:/Example/Example-b3-1/uart_regs/sim/funcsim/uart_regs_h.vwf" "" { Waveform "D:/Example/Example-b3-1/uart_regs/sim/funcsim/uart_regs_h.vwf" "tf_push" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_FOUND" "" "Info: Inverted registers were found during simulation" { { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_regs\|iir\[0\] " "Info: Register: \|uart_regs\|iir\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_regs\|lcr\[0\] " "Info: Register: \|uart_regs\|lcr\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_regs\|lcr\[1\] " "Info: Register: \|uart_regs\|lcr\[1\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_regs\|lsr5r " "Info: Register: \|uart_regs\|lsr5r" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_regs\|lsr6r " "Info: Register: \|uart_regs\|lsr6r" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_regs\|uart_transmitter:transmitter\|stx_o_tmp " "Info: Register: \|uart_regs\|uart_transmitter:transmitter\|stx_o_tmp" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_regs\|fcr\[1\] " "Info: Register: \|uart_regs\|fcr\[1\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_regs\|fcr\[0\] " "Info: Register: \|uart_regs\|fcr\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_regs\|lsr5_d " "Info: Register: \|uart_regs\|lsr5_d" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_regs\|lsr6_d " "Info: Register: \|uart_regs\|lsr6_d" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_regs\|uart_receiver:receiver\|Selector17~255 " "Info: Register: \|uart_regs\|uart_receiver:receiver\|Selector17~255" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|uart_regs\|serial_delay " "Info: Register: \|uart_regs\|serial_delay" {  } {  } 0 0 "Register: %1!s!" 0 0}  } {  } 0 0 "Inverted registers were found during simulation" 0 0}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0}  } {  } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0}
{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" {  } {  } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "      5.73 % " "Info: Simulation coverage is       5.73 %" {  } {  } 0 0 "Simulation coverage is %1!s!" 0 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "16796 " "Info: Number of transitions in simulation is 16796" {  } {  } 0 0 "Number of transitions in simulation is %1!s!" 0 0}
{ "Info" "ISDB_SDB_PROMOTE_WRITE_BINARY_VECTOR" "uart_regs.sim.vwf " "Info: Vector file uart_regs.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." {  } {  } 0 0 "Vector file %1!s! is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 1  Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 08 10:37:30 2008 " "Info: Processing ended: Sat Nov 08 10:37:30 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}