uart_regs.fnsim.qmsg

ALTER FPGA/GPLD设计（初级篇）的源码

{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "rbit_in uart_receiver.v(38) " "Warning (10036): Verilog HDL or VHDL warning at uart_receiver.v(38): object \"rbit_in\" assigned a value but never read" {  } { { "../src/uart_receiver.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_receiver.v" 38 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "rcounter16_eq_1 uart_receiver.v(72) " "Warning (10036): Verilog HDL or VHDL warning at uart_receiver.v(72): object \"rcounter16_eq_1\" assigned a value but never read" {  } { { "../src/uart_receiver.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_receiver.v" 72 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "rbit_in uart_receiver.v(38) " "Info (10041): Verilog HDL or VHDL info at uart_receiver.v(38): inferred latch for \"rbit_in\"" {  } { { "../src/uart_receiver.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_receiver.v" 38 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 uart_receiver.v(206) " "Warning (10230): Verilog HDL assignment warning at uart_receiver.v(206): truncated value with size 32 to match size of target (8)" {  } { { "../src/uart_receiver.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_receiver.v" 206 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 uart_receiver.v(221) " "Warning (10230): Verilog HDL assignment warning at uart_receiver.v(221): truncated value with size 32 to match size of target (10)" {  } { { "../src/uart_receiver.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_receiver.v" 221 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "myfifo_10 uart_receiver:receiver\|myfifo_10:myfifo_u " "Info: Elaborating entity \"myfifo_10\" for hierarchy \"uart_receiver:receiver\|myfifo_10:myfifo_u\"" {  } { { "../src/uart_receiver.v" "myfifo_u" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_receiver.v" 66 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component " "Info: Elaborating entity \"scfifo\" for hierarchy \"uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\"" {  } { { "../core/myfifo_10.v" "scfifo_component" { Text "D:/Example/Example-b3-1/uart_regs/core/myfifo_10.v" 89 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component " "Info: Elaborated megafunction instantiation \"uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\"" {  } { { "../core/myfifo_10.v" "" { Text "D:/Example/Example-b3-1/uart_regs/core/myfifo_10.v" 89 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_c751.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/scfifo_c751.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_c751 " "Info: Found entity 1: scfifo_c751" {  } { { "db/scfifo_c751.tdf" "" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/scfifo_c751.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_c751 uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated " "Info: Elaborating entity \"scfifo_c751\" for hierarchy \"uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\"" {  } { { "scfifo.tdf" "auto_generated" { Text "e:/quartusii6.0/libraries/megafunctions/scfifo.tdf" 294 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_jd51.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_jd51.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_jd51 " "Info: Found entity 1: a_dpfifo_jd51" {  } { { "db/a_dpfifo_jd51.tdf" "" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/a_dpfifo_jd51.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_jd51 uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo " "Info: Elaborating entity \"a_dpfifo_jd51\" for hierarchy \"uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo\"" {  } { { "db/scfifo_c751.tdf" "dpfifo" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/scfifo_c751.tdf" 37 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_nb21.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dpram_nb21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_nb21 " "Info: Found entity 1: dpram_nb21" {  } { { "db/dpram_nb21.tdf" "" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/dpram_nb21.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_nb21 uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo\|dpram_nb21:FIFOram " "Info: Elaborating entity \"dpram_nb21\" for hierarchy \"uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo\|dpram_nb21:FIFOram\"" {  } { { "db/a_dpfifo_jd51.tdf" "FIFOram" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/a_dpfifo_jd51.tdf" 43 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4pl1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_4pl1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4pl1 " "Info: Found entity 1: altsyncram_4pl1" {  } { { "db/altsyncram_4pl1.tdf" "" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/altsyncram_4pl1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4pl1 uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo\|dpram_nb21:FIFOram\|altsyncram_4pl1:altsyncram1 " "Info: Elaborating entity \"altsyncram_4pl1\" for hierarchy \"uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo\|dpram_nb21:FIFOram\|altsyncram_4pl1:altsyncram1\"" {  } { { "db/dpram_nb21.tdf" "altsyncram1" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/dpram_nb21.tdf" 36 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartusii6.0/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/quartusii6.0/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartusii6.0/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 373 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartusii6.0/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/quartusii6.0/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "e:/quartusii6.0/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartusii6.0/libraries/megafunctions/lpm_add_sub.tdf" 266 4 0 } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 373 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Info: Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 17 " "Info: Parameter \"LPM_WIDTH\" = \"17\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 373 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartusii6.0/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/quartusii6.0/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "e:/quartusii6.0/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "e:/quartusii6.0/libraries/megafunctions/addcore.tdf" 94 2 0 } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 373 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}