uart_regs.hif

ALTER FPGA/GPLD设计（初级篇）的源码

Version 6.0 Build 178 04/27/2006 SJ Full Version
39
1951
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
uart_regs
# storage
db|uart_regs.(0).cnf
db|uart_regs.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|src|uart_regs.v
daa4242bb9e4cdee38f5ea301ac37e22
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
..|src|uart_defines.v
c44ef790f8799c3269b4e5e5df7f7f7
}
# hierarchies {
|
}
# end
# entity
uart_transmitter
# storage
db|uart_regs.(1).cnf
db|uart_regs.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|src|uart_transmitter.v
582bc8b47382edfdfec7f088fc8279
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
s_idle
000
PARAMETER_BIN
DEF
s_send_start
001
PARAMETER_BIN
DEF
s_send_byte
010
PARAMETER_BIN
DEF
s_send_parity
011
PARAMETER_BIN
DEF
s_send_stop
100
PARAMETER_BIN
DEF
s_pop_byte
101
PARAMETER_BIN
DEF
}
# include_file {
..|src|uart_defines.v
c44ef790f8799c3269b4e5e5df7f7f7
}
# hierarchies {
uart_transmitter:transmitter
}
# end
# entity
myfifo_8
# storage
db|uart_regs.(2).cnf
db|uart_regs.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|core|myfifo_8.v
d23f503787aa02f3d4bb76a4e21441
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
uart_transmitter:transmitter|myfifo_8:myfifo_u1
}
# end
# entity
scfifo
# storage
db|uart_regs.(3).cnf
db|uart_regs.(3).cnf
# case_insensitive
# source_file
e:|quartusii6.0|libraries|megafunctions|scfifo.tdf
b67e14bc943b20b2659e8ef1077457
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
8
PARAMETER_DEC
USR
LPM_NUMWORDS
16
PARAMETER_DEC
USR
LPM_WIDTHU
4
PARAMETER_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
USR
ALMOST_FULL_VALUE
0
PARAMETER_UNKNOWN
DEF
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_3651
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw
-1
3
rdreq
-1
3
q
-1
3
full
-1
3
empty
-1
3
data
-1
3
clock
-1
3
aclr
-1
3
}
# include_file {
e:|quartusii6.0|libraries|megafunctions|a_regfifo.inc
afe6bfc54c15224ce61beaea9e71dc
e:|quartusii6.0|libraries|megafunctions|a_dpfifo.inc
748303753a041187a5d4113b5f62acf
e:|quartusii6.0|libraries|megafunctions|a_i2fifo.inc
ca5bb76c5a51df22b24c8b01cbcc918
e:|quartusii6.0|libraries|megafunctions|a_fffifo.inc
ebf62e69b8fb10b5db33a57861298d55
e:|quartusii6.0|libraries|megafunctions|a_f2fifo.inc
9bc132bd4e9e2ef1fb9633f6a742f
e:|quartusii6.0|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
}
# hierarchies {
uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component
}
# end
# entity
scfifo_3651
# storage
db|uart_regs.(4).cnf
db|uart_regs.(4).cnf
# case_insensitive
# source_file
db|scfifo_3651.tdf
222f919f3198c840c9021d756873326
6
# used_port {
wrreq
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated
}
# end
# entity
a_dpfifo_ac51
# storage
db|uart_regs.(5).cnf
db|uart_regs.(5).cnf
# case_insensitive
# source_file
db|a_dpfifo_ac51.tdf
569291c14f79565ce5adee5793f1c1c
6
# used_port {
wreq
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo
}
# end
# entity
a_fefifo_66f
# storage
db|uart_regs.(6).cnf
db|uart_regs.(6).cnf
# case_insensitive
# source_file
db|a_fefifo_66f.tdf
165a608613f0ecb3e3a95b98ca789e2
6
# used_port {
wreq
-1
3
usedw_out3
-1
3
usedw_out2
-1
3
usedw_out1
-1
3
usedw_out0
-1
3
sclr
-1
3
rreq
-1
3
full
-1
3
empty
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|a_fefifo_66f:fifo_state
uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|a_fefifo_66f:fifo_state
}
# end
# entity
cntr_9d7
# storage
db|uart_regs.(7).cnf
db|uart_regs.(7).cnf
# case_insensitive
# source_file
db|cntr_9d7.tdf
b8eedc92ba237e0892a19729ab91c
6
# used_port {
updown
-1
3
sclr
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|a_fefifo_66f:fifo_state|cntr_9d7:count_usedw
uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|a_fefifo_66f:fifo_state|cntr_9d7:count_usedw
}
# end
# entity
dpram_ea21
# storage
db|uart_regs.(8).cnf
db|uart_regs.(8).cnf
# case_insensitive
# source_file
db|dpram_ea21.tdf
791ca567b177cc181b928baf85497fa
6
# used_port {
wren
-1
3
wraddress3
-1
3
wraddress2
-1
3
wraddress1
-1
3
wraddress0
-1
3
rdaddress3
-1
3
rdaddress2
-1
3
rdaddress1
-1
3
rdaddress0
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
outclocken
-1
3
outclock
-1
3
inclock
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|dpram_ea21:FIFOram
}
# end
# entity
altsyncram_gml1
# storage
db|uart_regs.(9).cnf
db|uart_regs.(9).cnf
# case_insensitive
# source_file
db|altsyncram_gml1.tdf
4d3ce7c49a3eeadd7209f12fbdd3734
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# hierarchies {
uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|dpram_ea21:FIFOram|altsyncram_gml1:altsyncram1
}
# end
# entity
cntr_re8
# storage
db|uart_regs.(10).cnf
db|uart_regs.(10).cnf
# case_insensitive
# source_file
db|cntr_re8.tdf
6a31614b2b2bd7173099ad88b71a98
6
# used_port {
sclr
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|cntr_re8:rd_ptr_count
uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_3651:auto_generated|a_dpfifo_ac51:dpfifo|cntr_re8:wr_ptr
uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|cntr_re8:rd_ptr_count
uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|cntr_re8:wr_ptr
}
# end
# entity
uart_receiver
# storage
db|uart_regs.(11).cnf
db|uart_regs.(11).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|src|uart_receiver.v
2c7a24d23e91828ee6d67d837b939dbf
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sr_idle
000
PARAMETER_BIN
DEF
sr_rec_start
001
PARAMETER_BIN
DEF
sr_rec_bit
010
PARAMETER_BIN
DEF
sr_rec_stop
100
PARAMETER_BIN
DEF
sr_rec_prepare
011
PARAMETER_BIN
DEF
sr_end_bit
101
PARAMETER_BIN
DEF
sr_push
110
PARAMETER_BIN
DEF
sr_temp
111
PARAMETER_BIN
DEF
}
# hierarchies {
uart_receiver:receiver
}
# end
# entity
myfifo_10
# storage
db|uart_regs.(12).cnf
db|uart_regs.(12).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|core|myfifo_10.v
4f238b1f46758d92aee3e148d28b38eb
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
uart_receiver:receiver|myfifo_10:myfifo_u
}
# end
# entity
scfifo
# storage
db|uart_regs.(13).cnf
db|uart_regs.(13).cnf
# case_insensitive
# source_file
e:|quartusii6.0|libraries|megafunctions|scfifo.tdf
b67e14bc943b20b2659e8ef1077457
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
10
PARAMETER_DEC
USR
LPM_NUMWORDS
16
PARAMETER_DEC
USR
LPM_WIDTHU
4
PARAMETER_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
USR
ALMOST_FULL_VALUE
0
PARAMETER_UNKNOWN
DEF
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_c751
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw
-1
3
rdreq
-1
3
q
-1
3
full
-1
3
empty
-1
3
data
-1
3
clock
-1
3
aclr
-1
3
}
# include_file {
e:|quartusii6.0|libraries|megafunctions|a_regfifo.inc
afe6bfc54c15224ce61beaea9e71dc
e:|quartusii6.0|libraries|megafunctions|a_dpfifo.inc
748303753a041187a5d4113b5f62acf
e:|quartusii6.0|libraries|megafunctions|a_i2fifo.inc
ca5bb76c5a51df22b24c8b01cbcc918
e:|quartusii6.0|libraries|megafunctions|a_fffifo.inc
ebf62e69b8fb10b5db33a57861298d55
e:|quartusii6.0|libraries|megafunctions|a_f2fifo.inc
9bc132bd4e9e2ef1fb9633f6a742f
e:|quartusii6.0|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
}
# hierarchies {
uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component
}
# end
# entity
scfifo_c751
# storage
db|uart_regs.(14).cnf
db|uart_regs.(14).cnf
# case_insensitive
# source_file
db|scfifo_c751.tdf
401ad08eb798d4bf9a9133ac7540bf
6
# used_port {
wrreq
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated
}
# end
# entity
a_dpfifo_jd51
# storage
db|uart_regs.(15).cnf
db|uart_regs.(15).cnf
# case_insensitive
# source_file
db|a_dpfifo_jd51.tdf
6bf9cfb8675622ab0d07e7cc1f37e3b
6
# used_port {
wreq
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo
}
# end
# entity
dpram_nb21
# storage
db|uart_regs.(16).cnf
db|uart_regs.(16).cnf
# case_insensitive
# source_file
db|dpram_nb21.tdf
b71f97e69d71fe734a879b75bd8ee193
6
# used_port {
wren
-1
3
wraddress3
-1
3
wraddress2
-1
3
wraddress1
-1
3
wraddress0
-1
3
rdaddress3
-1
3
rdaddress2
-1
3
rdaddress1
-1
3
rdaddress0
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
outclocken
-1
3
outclock
-1
3
inclock
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|dpram_nb21:FIFOram
}
# end
# entity
altsyncram_4pl1
# storage
db|uart_regs.(17).cnf
db|uart_regs.(17).cnf
# case_insensitive
# source_file
db|altsyncram_4pl1.tdf
4ada6c4f43576ba77f38e70eb48efad
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# hierarchies {
uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|dpram_nb21:FIFOram|altsyncram_4pl1:altsyncram1
}
# end
# complete