uart_regs.tan.qmsg

ALTER FPGA/GPLD设计（初级篇）的源码

{ "Info" "ITDB_FULL_SLACK_RESULT" "wb_we_i pin wb_addr_i\[0\] register dl\[7\] 8.854 ns " "Info: Slack time is 8.854 ns for clock \"wb_we_i\" between source pin \"wb_addr_i\[0\]\" and destination register \"dl\[7\]\"" { { "Info" "ITDB_FULL_TSU_REQUIREMENT" "12.000 ns + register " "Info: + tsu requirement for source pin and destination register is 12.000 ns" {  } {  } 0 0 "%2!c! tsu requirement for source pin and destination %3!s! is %1!s!" 0 0} { "Info" "ITDB_SLACK_TSU_RESULT" "3.146 ns - " "Info: - tsu from clock to input pin is 3.146 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.165 ns + Longest pin register " "Info: + Longest pin to register delay is 6.165 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns wb_addr_i\[0\] 1 PIN PIN_A20 17 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A20; Fanout = 17; PIN Node = 'wb_addr_i\[0\]'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { wb_addr_i[0] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.239 ns) + CELL(0.459 ns) 3.839 ns Selector6~197 2 COMB LC_X28_Y25_N8 8 " "Info: 2: + IC(2.239 ns) + CELL(0.459 ns) = 3.839 ns; Loc. = LC_X28_Y25_N8; Fanout = 8; COMB Node = 'Selector6~197'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "2.698 ns" { wb_addr_i[0] Selector6~197 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 122 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.087 ns) 4.065 ns dl\[0\]~15 3 COMB LC_X28_Y25_N9 8 " "Info: 3: + IC(0.139 ns) + CELL(0.087 ns) = 4.065 ns; Loc. = LC_X28_Y25_N9; Fanout = 8; COMB Node = 'dl\[0\]~15'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "0.226 ns" { Selector6~197 dl[0]~15 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 226 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.374 ns) + CELL(0.726 ns) 6.165 ns dl\[7\] 4 REG LC_X29_Y23_N3 3 " "Info: 4: + IC(1.374 ns) + CELL(0.726 ns) = 6.165 ns; Loc. = LC_X29_Y23_N3; Fanout = 3; REG Node = 'dl\[7\]'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "2.100 ns" { dl[0]~15 dl[7] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 226 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.413 ns ( 39.14 % ) " "Info: Total cell delay = 2.413 ns ( 39.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.752 ns ( 60.86 % ) " "Info: Total interconnect delay = 3.752 ns ( 60.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "6.165 ns" { wb_addr_i[0] Selector6~197 dl[0]~15 dl[7] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "6.165 ns" { wb_addr_i[0] wb_addr_i[0]~out0 Selector6~197 dl[0]~15 dl[7] } { 0.000ns 0.000ns 2.239ns 0.139ns 1.374ns } { 0.000ns 1.141ns 0.459ns 0.087ns 0.726ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 226 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wb_we_i destination 3.029 ns - Shortest register " "Info: - Shortest clock path from clock \"wb_we_i\" to destination register is 3.029 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns wb_we_i 1 CLK PIN_N3 43 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_N3; Fanout = 43; CLK Node = 'wb_we_i'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { wb_we_i } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.709 ns) + CELL(0.560 ns) 3.029 ns dl\[7\] 2 REG LC_X29_Y23_N3 3 " "Info: 2: + IC(1.709 ns) + CELL(0.560 ns) = 3.029 ns; Loc. = LC_X29_Y23_N3; Fanout = 3; REG Node = 'dl\[7\]'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "2.269 ns" { wb_we_i dl[7] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 226 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 43.58 % ) " "Info: Total cell delay = 1.320 ns ( 43.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.709 ns ( 56.42 % ) " "Info: Total interconnect delay = 1.709 ns ( 56.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.029 ns" { wb_we_i dl[7] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.029 ns" { wb_we_i wb_we_i~out0 dl[7] } { 0.000ns 0.000ns 1.709ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "6.165 ns" { wb_addr_i[0] Selector6~197 dl[0]~15 dl[7] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "6.165 ns" { wb_addr_i[0] wb_addr_i[0]~out0 Selector6~197 dl[0]~15 dl[7] } { 0.000ns 0.000ns 2.239ns 0.139ns 1.374ns } { 0.000ns 1.141ns 0.459ns 0.087ns 0.726ns } } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.029 ns" { wb_we_i dl[7] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.029 ns" { wb_we_i wb_we_i~out0 dl[7] } { 0.000ns 0.000ns 1.709ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "%2!c! tsu from clock to input pin is %1!s!" 0 0}  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "6.165 ns" { wb_addr_i[0] Selector6~197 dl[0]~15 dl[7] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "6.165 ns" { wb_addr_i[0] wb_addr_i[0]~out0 Selector6~197 dl[0]~15 dl[7] } { 0.000ns 0.000ns 2.239ns 0.139ns 1.374ns } { 0.000ns 1.141ns 0.459ns 0.087ns 0.726ns } } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.029 ns" { wb_we_i dl[7] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.029 ns" { wb_we_i wb_we_i~out0 dl[7] } { 0.000ns 0.000ns 1.709ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk wb_dat_o\[2\] uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo\|dpram_nb21:FIFOram\|altsyncram_4pl1:altsyncram1\|ram_block2a2~portb_address_reg0 16.657 ns memory " "Info: tco from clock \"clk\" to destination pin \"wb_dat_o\[2\]\" through memory \"uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo\|dpram_nb21:FIFOram\|altsyncram_4pl1:altsyncram1\|ram_block2a2~portb_address_reg0\" is 16.657 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.184 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 3.184 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.020 ns) 1.020 ns clk 1 CLK PIN_A15 209 " "Info: 1: + IC(0.000 ns) + CELL(1.020 ns) = 1.020 ns; Loc. = PIN_A15; Fanout = 209; CLK Node = 'clk'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.781 ns) + CELL(0.383 ns) 3.184 ns uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo\|dpram_nb21:FIFOram\|altsyncram_4pl1:altsyncram1\|ram_block2a2~portb_address_reg0 2 MEM M512_X26_Y24 10 " "Info: 2: + IC(1.781 ns) + CELL(0.383 ns) = 3.184 ns; Loc. = M512_X26_Y24; Fanout = 10; MEM Node = 'uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo\|dpram_nb21:FIFOram\|altsyncram_4pl1:altsyncram1\|ram_block2a2~portb_address_reg0'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "2.164 ns" { clk uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|dpram_nb21:FIFOram|altsyncram_4pl1:altsyncram1|ram_block2a2~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_4pl1.tdf" "" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/altsyncram_4pl1.tdf" 108 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.403 ns ( 44.06 % ) " "Info: Total cell delay = 1.403 ns ( 44.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.781 ns ( 55.94 % ) " "Info: Total interconnect delay = 1.781 ns ( 55.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.184 ns" { clk uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|dpram_nb21:FIFOram|altsyncram_4pl1:altsyncram1|ram_block2a2~portb_address_reg0 } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.184 ns" { clk clk~out0 uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|dpram_nb21:FIFOram|altsyncram_4pl1:altsyncram1|ram_block2a2~portb_address_reg0 } { 0.000ns 0.000ns 1.781ns } { 0.000ns 1.020ns 0.383ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.519 ns + " "Info: + Micro clock to output delay of source is 0.519 ns" {  } { { "db/altsyncram_4pl1.tdf" "" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/altsyncram_4pl1.tdf" 108 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.954 ns + Longest memory pin " "Info: + Longest memory to pin delay is 12.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo\|dpram_nb21:FIFOram\|altsyncram_4pl1:altsyncram1\|ram_block2a2~portb_address_reg0 1 MEM M512_X26_Y24 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X26_Y24; Fanout = 10; MEM Node = 'uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo\|dpram_nb21:FIFOram\|altsyncram_4pl1:altsyncram1\|ram_block2a2~portb_address_reg0'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|dpram_nb21:FIFOram|altsyncram_4pl1:altsyncram1|ram_block2a2~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_4pl1.tdf" "" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/altsyncram_4pl1.tdf" 108 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.066 ns) 3.066 ns uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo\|dpram_nb21:FIFOram\|altsyncram_4pl1:altsyncram1\|q_b\[4\] 2 MEM M512_X26_Y24 1 " "Info: 2: + IC(0.000 ns) + CELL(3.066 ns) = 3.066 ns; Loc. = M512_X26_Y24; Fanout = 1; MEM Node = 'uart_receiver:receiver\|myfifo_10:myfifo_u\|scfifo:scfifo_component\|scfifo_c751:auto_generated\|a_dpfifo_jd51:dpfifo\|dpram_nb21:FIFOram\|altsyncram_4pl1:altsyncram1\|q_b\[4\]'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.066 ns" { uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|dpram_nb21:FIFOram|altsyncram_4pl1:altsyncram1|ram_block2a2~portb_address_reg0 uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|dpram_nb21:FIFOram|altsyncram_4pl1:altsyncram1|q_b[4] } "NODE_NAME" } } { "db/altsyncram_4pl1.tdf" "" { Text "D:/Example/Example-b3-1/uart_regs/dev/db/altsyncram_4pl1.tdf" 44 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.256 ns) + CELL(0.332 ns) 4.654 ns wb_dat_o~94 3 COMB LC_X29_Y23_N8 1 " "Info: 3: + IC(1.256 ns) + CELL(0.332 ns) = 4.654 ns; Loc. = LC_X29_Y23_N8; Fanout = 1; COMB Node = 'wb_dat_o~94'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "1.588 ns" { uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|dpram_nb21:FIFOram|altsyncram_4pl1:altsyncram1|q_b[4] wb_dat_o~94 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.053 ns) + CELL(0.087 ns) 5.794 ns Selector5~59 4 COMB LC_X29_Y24_N0 1 " "Info: 4: + IC(1.053 ns) + CELL(0.087 ns) = 5.794 ns; Loc. = LC_X29_Y24_N0; Fanout = 1; COMB Node = 'Selector5~59'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "1.140 ns" { wb_dat_o~94 Selector5~59 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 122 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.352 ns) + CELL(0.332 ns) 6.478 ns Selector5~60 5 COMB LC_X29_Y24_N4 1 " "Info: 5: + IC(0.352 ns) + CELL(0.332 ns) = 6.478 ns; Loc. = LC_X29_Y24_N4; Fanout = 1; COMB Node = 'Selector5~60'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "0.684 ns" { Selector5~59 Selector5~60 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 122 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.078 ns) + CELL(0.332 ns) 7.888 ns Selector5~61 6 COMB LC_X29_Y23_N1 1 " "Info: 6: + IC(1.078 ns) + CELL(0.332 ns) = 7.888 ns; Loc. = LC_X29_Y23_N1; Fanout = 1; COMB Node = 'Selector5~61'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "1.410 ns" { Selector5~60 Selector5~61 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 122 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.562 ns) + CELL(2.504 ns) 12.954 ns wb_dat_o\[2\] 7 PIN PIN_AB19 0 " "Info: 7: + IC(2.562 ns) + CELL(2.504 ns) = 12.954 ns; Loc. = PIN_AB19; Fanout = 0; PIN Node = 'wb_dat_o\[2\]'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "5.066 ns" { Selector5~61 wb_dat_o[2] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.653 ns ( 51.36 % ) " "Info: Total cell delay = 6.653 ns ( 51.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.301 ns ( 48.64 % ) " "Info: Total interconnect delay = 6.301 ns ( 48.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "12.954 ns" { uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|dpram_nb21:FIFOram|altsyncram_4pl1:altsyncram1|ram_block2a2~portb_address_reg0 uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|dpram_nb21:FIFOram|altsyncram_4pl1:altsyncram1|q_b[4] wb_dat_o~94 Selector5~59 Selector5~60 Selector5~61 wb_dat_o[2] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "12.954 ns" { uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|dpram_nb21:FIFOram|altsyncram_4pl1:altsyncram1|ram_block2a2~portb_address_reg0 uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|dpram_nb21:FIFOram|altsyncram_4pl1:altsyncram1|q_b[4] wb_dat_o~94 Selector5~59 Selector5~60 Selector5~61 wb_dat_o[2] } { 0.000ns 0.000ns 1.256ns 1.053ns 0.352ns 1.078ns 2.562ns } { 0.000ns 3.066ns 0.332ns 0.087ns 0.332ns 0.332ns 2.504ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.184 ns" { clk uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|dpram_nb21:FIFOram|altsyncram_4pl1:altsyncram1|ram_block2a2~portb_address_reg0 } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.184 ns" { clk clk~out0 uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|dpram_nb21:FIFOram|altsyncram_4pl1:altsyncram1|ram_block2a2~portb_address_reg0 } { 0.000ns 0.000ns 1.781ns } { 0.000ns 1.020ns 0.383ns } } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "12.954 ns" { uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|dpram_nb21:FIFOram|altsyncram_4pl1:altsyncram1|ram_block2a2~portb_address_reg0 uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|dpram_nb21:FIFOram|altsyncram_4pl1:altsyncram1|q_b[4] wb_dat_o~94 Selector5~59 Selector5~60 Selector5~61 wb_dat_o[2] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "12.954 ns" { uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|dpram_nb21:FIFOram|altsyncram_4pl1:altsyncram1|ram_block2a2~portb_address_reg0 uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_c751:auto_generated|a_dpfifo_jd51:dpfifo|dpram_nb21:FIFOram|altsyncram_4pl1:altsyncram1|q_b[4] wb_dat_o~94 Selector5~59 Selector5~60 Selector5~61 wb_dat_o[2] } { 0.000ns 0.000ns 1.256ns 1.053ns 0.352ns 1.078ns 2.562ns } { 0.000ns 3.066ns 0.332ns 0.087ns 0.332ns 0.332ns 2.504ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "wb_addr_i\[2\] wb_dat_o\[3\] 17.064 ns Longest " "Info: Longest tpd from source pin \"wb_addr_i\[2\]\" to destination pin \"wb_dat_o\[3\]\" is 17.064 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns wb_addr_i\[2\] 1 PIN PIN_A24 21 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A24; Fanout = 21; PIN Node = 'wb_addr_i\[2\]'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { wb_addr_i[2] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.878 ns) + CELL(0.087 ns) 7.106 ns Selector6~199 2 COMB LC_X29_Y23_N2 5 " "Info: 2: + IC(5.878 ns) + CELL(0.087 ns) = 7.106 ns; Loc. = LC_X29_Y23_N2; Fanout = 5; COMB Node = 'Selector6~199'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "5.965 ns" { wb_addr_i[2] Selector6~199 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 122 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.365 ns) + CELL(0.087 ns) 8.558 ns Selector4~75 3 COMB LC_X27_Y24_N3 1 " "Info: 3: + IC(1.365 ns) + CELL(0.087 ns) = 8.558 ns; Loc. = LC_X27_Y24_N3; Fanout = 1; COMB Node = 'Selector4~75'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "1.452 ns" { Selector6~199 Selector4~75 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 122 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.357 ns) + CELL(0.459 ns) 9.374 ns Selector4~76 4 COMB LC_X27_Y24_N2 1 " "Info: 4: + IC(0.357 ns) + CELL(0.459 ns) = 9.374 ns; Loc. = LC_X27_Y24_N2; Fanout = 1; COMB Node = 'Selector4~76'" {  } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "0.816 ns" { Selector4~75 Selector4~76 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 122 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.348 ns) + CELL(0.087 ns) 9.809 ns Selector4~77 5 COMB LC_X27_Y24_N5 1 " "Info: 5: + IC(0.348 ns) + CELL(0.087 ns) = 9.809 ns; Loc. =