📄 uart_regs.tan.qmsg
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{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register dlc\[12\] register dlc\[15\] 2.29 ns " "Info: Slack time is 2.29 ns for clock \"clk\" between source register \"dlc\[12\]\" and destination register \"dlc\[15\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "185.12 MHz 5.402 ns " "Info: Fmax is 185.12 MHz (period= 5.402 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "7.506 ns + Largest register register " "Info: + Largest register to register requirement is 7.506 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "7.692 ns + " "Info: + Setup relationship between source and destination is 7.692 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 7.692 ns " "Info: + Latch edge is 7.692 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 7.692 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clk\" is 7.692 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 7.692 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clk\" is 7.692 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.327 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.327 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.020 ns) 1.020 ns clk 1 CLK PIN_A15 209 " "Info: 1: + IC(0.000 ns) + CELL(1.020 ns) = 1.020 ns; Loc. = PIN_A15; Fanout = 209; CLK Node = 'clk'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.747 ns) + CELL(0.560 ns) 3.327 ns dlc\[15\] 2 REG LC_X30_Y24_N7 2 " "Info: 2: + IC(1.747 ns) + CELL(0.560 ns) = 3.327 ns; Loc. = LC_X30_Y24_N7; Fanout = 2; REG Node = 'dlc\[15\]'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "2.307 ns" { clk dlc[15] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 369 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.580 ns ( 47.49 % ) " "Info: Total cell delay = 1.580 ns ( 47.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.747 ns ( 52.51 % ) " "Info: Total interconnect delay = 1.747 ns ( 52.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.327 ns" { clk dlc[15] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.327 ns" { clk clk~out0 dlc[15] } { 0.000ns 0.000ns 1.747ns } { 0.000ns 1.020ns 0.560ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.327 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.327 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.020 ns) 1.020 ns clk 1 CLK PIN_A15 209 " "Info: 1: + IC(0.000 ns) + CELL(1.020 ns) = 1.020 ns; Loc. = PIN_A15; Fanout = 209; CLK Node = 'clk'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.747 ns) + CELL(0.560 ns) 3.327 ns dlc\[12\] 2 REG LC_X30_Y24_N4 2 " "Info: 2: + IC(1.747 ns) + CELL(0.560 ns) = 3.327 ns; Loc. = LC_X30_Y24_N4; Fanout = 2; REG Node = 'dlc\[12\]'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "2.307 ns" { clk dlc[12] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 369 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.580 ns ( 47.49 % ) " "Info: Total cell delay = 1.580 ns ( 47.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.747 ns ( 52.51 % ) " "Info: Total interconnect delay = 1.747 ns ( 52.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.327 ns" { clk dlc[12] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.327 ns" { clk clk~out0 dlc[12] } { 0.000ns 0.000ns 1.747ns } { 0.000ns 1.020ns 0.560ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.327 ns" { clk dlc[15] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.327 ns" { clk clk~out0 dlc[15] } { 0.000ns 0.000ns 1.747ns } { 0.000ns 1.020ns 0.560ns } } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.327 ns" { clk dlc[12] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.327 ns" { clk clk~out0 dlc[12] } { 0.000ns 0.000ns 1.747ns } { 0.000ns 1.020ns 0.560ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns - " "Info: - Micro clock to output delay of source is 0.176 ns" { } { { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 369 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns - " "Info: - Micro setup delay of destination is 0.010 ns" { } { { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 369 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.327 ns" { clk dlc[15] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.327 ns" { clk clk~out0 dlc[15] } { 0.000ns 0.000ns 1.747ns } { 0.000ns 1.020ns 0.560ns } } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.327 ns" { clk dlc[12] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.327 ns" { clk clk~out0 dlc[12] } { 0.000ns 0.000ns 1.747ns } { 0.000ns 1.020ns 0.560ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.216 ns - Longest register register " "Info: - Longest register to register delay is 5.216 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dlc\[12\] 1 REG LC_X30_Y24_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X30_Y24_N4; Fanout = 2; REG Node = 'dlc\[12\]'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { dlc[12] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 369 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.439 ns) + CELL(0.459 ns) 0.898 ns WideOr1~115 2 COMB LC_X30_Y24_N9 1 " "Info: 2: + IC(0.439 ns) + CELL(0.459 ns) = 0.898 ns; Loc. = LC_X30_Y24_N9; Fanout = 1; COMB Node = 'WideOr1~115'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "0.898 ns" { dlc[12] WideOr1~115 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.085 ns) + CELL(0.213 ns) 2.196 ns WideOr1~116 3 COMB LC_X30_Y25_N0 17 " "Info: 3: + IC(1.085 ns) + CELL(0.213 ns) = 2.196 ns; Loc. = LC_X30_Y25_N0; Fanout = 17; COMB Node = 'WideOr1~116'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "1.298 ns" { WideOr1~115 WideOr1~116 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 372 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.129 ns) + CELL(0.087 ns) 3.412 ns Add0~953 4 COMB LC_X31_Y24_N8 3 " "Info: 4: + IC(1.129 ns) + CELL(0.087 ns) = 3.412 ns; Loc. = LC_X31_Y24_N8; Fanout = 3; COMB Node = 'Add0~953'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "1.216 ns" { WideOr1~116 Add0~953 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 373 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.538 ns) + CELL(0.344 ns) 4.294 ns dlc\[8\]~232 5 COMB LC_X30_Y24_N0 2 " "Info: 5: + IC(0.538 ns) + CELL(0.344 ns) = 4.294 ns; Loc. = LC_X30_Y24_N0; Fanout = 2; COMB Node = 'dlc\[8\]~232'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "0.882 ns" { Add0~953 dlc[8]~232 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 369 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 4.354 ns dlc\[9\]~233 6 COMB LC_X30_Y24_N1 2 " "Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 4.354 ns; Loc. = LC_X30_Y24_N1; Fanout = 2; COMB Node = 'dlc\[9\]~233'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "0.060 ns" { dlc[8]~232 dlc[9]~233 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 369 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 4.414 ns dlc\[10\]~234 7 COMB LC_X30_Y24_N2 2 " "Info: 7: + IC(0.000 ns) + CELL(0.060 ns) = 4.414 ns; Loc. = LC_X30_Y24_N2; Fanout = 2; COMB Node = 'dlc\[10\]~234'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "0.060 ns" { dlc[9]~233 dlc[10]~234 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 369 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 4.474 ns dlc\[11\]~235 8 COMB LC_X30_Y24_N3 2 " "Info: 8: + IC(0.000 ns) + CELL(0.060 ns) = 4.474 ns; Loc. = LC_X30_Y24_N3; Fanout = 2; COMB Node = 'dlc\[11\]~235'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "0.060 ns" { dlc[10]~234 dlc[11]~235 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 369 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.135 ns) 4.609 ns dlc\[12\]~236 9 COMB LC_X30_Y24_N4 3 " "Info: 9: + IC(0.000 ns) + CELL(0.135 ns) = 4.609 ns; Loc. = LC_X30_Y24_N4; Fanout = 3; COMB Node = 'dlc\[12\]~236'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "0.135 ns" { dlc[11]~235 dlc[12]~236 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 369 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.607 ns) 5.216 ns dlc\[15\] 10 REG LC_X30_Y24_N7 2 " "Info: 10: + IC(0.000 ns) + CELL(0.607 ns) = 5.216 ns; Loc. = LC_X30_Y24_N7; Fanout = 2; REG Node = 'dlc\[15\]'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "0.607 ns" { dlc[12]~236 dlc[15] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 369 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.025 ns ( 38.82 % ) " "Info: Total cell delay = 2.025 ns ( 38.82 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.191 ns ( 61.18 % ) " "Info: Total interconnect delay = 3.191 ns ( 61.18 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "5.216 ns" { dlc[12] WideOr1~115 WideOr1~116 Add0~953 dlc[8]~232 dlc[9]~233 dlc[10]~234 dlc[11]~235 dlc[12]~236 dlc[15] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "5.216 ns" { dlc[12] WideOr1~115 WideOr1~116 Add0~953 dlc[8]~232 dlc[9]~233 dlc[10]~234 dlc[11]~235 dlc[12]~236 dlc[15] } { 0.000ns 0.439ns 1.085ns 1.129ns 0.538ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.459ns 0.213ns 0.087ns 0.344ns 0.060ns 0.060ns 0.060ns 0.135ns 0.607ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.327 ns" { clk dlc[15] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.327 ns" { clk clk~out0 dlc[15] } { 0.000ns 0.000ns 1.747ns } { 0.000ns 1.020ns 0.560ns } } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.327 ns" { clk dlc[12] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.327 ns" { clk clk~out0 dlc[12] } { 0.000ns 0.000ns 1.747ns } { 0.000ns 1.020ns 0.560ns } } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "5.216 ns" { dlc[12] WideOr1~115 WideOr1~116 Add0~953 dlc[8]~232 dlc[9]~233 dlc[10]~234 dlc[11]~235 dlc[12]~236 dlc[15] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "5.216 ns" { dlc[12] WideOr1~115 WideOr1~116 Add0~953 dlc[8]~232 dlc[9]~233 dlc[10]~234 dlc[11]~235 dlc[12]~236 dlc[15] } { 0.000ns 0.439ns 1.085ns 1.129ns 0.538ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.459ns 0.213ns 0.087ns 0.344ns 0.060ns 0.060ns 0.060ns 0.135ns 0.607ns } } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "wb_we_i register lcr\[7\] register dl\[2\] 250.25 MHz 3.996 ns Internal " "Info: Clock \"wb_we_i\" has Internal fmax of 250.25 MHz between source register \"lcr\[7\]\" and destination register \"dl\[2\]\" (period= 3.996 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.820 ns + Longest register register " "Info: + Longest register to register delay is 3.820 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcr\[7\] 1 REG LC_X29_Y24_N9 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X29_Y24_N9; Fanout = 17; REG Node = 'lcr\[7\]'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { lcr[7] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 43 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.261 ns) + CELL(0.459 ns) 1.720 ns dl\[0\]~15 2 COMB LC_X28_Y25_N9 8 " "Info: 2: + IC(1.261 ns) + CELL(0.459 ns) = 1.720 ns; Loc. = LC_X28_Y25_N9; Fanout = 8; COMB Node = 'dl\[0\]~15'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "1.720 ns" { lcr[7] dl[0]~15 } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.374 ns) + CELL(0.726 ns) 3.820 ns dl\[2\] 3 REG LC_X29_Y23_N8 3 " "Info: 3: + IC(1.374 ns) + CELL(0.726 ns) = 3.820 ns; Loc. = LC_X29_Y23_N8; Fanout = 3; REG Node = 'dl\[2\]'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "2.100 ns" { dl[0]~15 dl[2] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.185 ns ( 31.02 % ) " "Info: Total cell delay = 1.185 ns ( 31.02 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.635 ns ( 68.98 % ) " "Info: Total interconnect delay = 2.635 ns ( 68.98 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.820 ns" { lcr[7] dl[0]~15 dl[2] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.820 ns" { lcr[7] dl[0]~15 dl[2] } { 0.000ns 1.261ns 1.374ns } { 0.000ns 0.459ns 0.726ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.010 ns - Smallest " "Info: - Smallest clock skew is 0.010 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wb_we_i destination 3.029 ns + Shortest register " "Info: + Shortest clock path from clock \"wb_we_i\" to destination register is 3.029 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns wb_we_i 1 CLK PIN_N3 43 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_N3; Fanout = 43; CLK Node = 'wb_we_i'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { wb_we_i } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.709 ns) + CELL(0.560 ns) 3.029 ns dl\[2\] 2 REG LC_X29_Y23_N8 3 " "Info: 2: + IC(1.709 ns) + CELL(0.560 ns) = 3.029 ns; Loc. = LC_X29_Y23_N8; Fanout = 3; REG Node = 'dl\[2\]'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "2.269 ns" { wb_we_i dl[2] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 226 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 43.58 % ) " "Info: Total cell delay = 1.320 ns ( 43.58 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.709 ns ( 56.42 % ) " "Info: Total interconnect delay = 1.709 ns ( 56.42 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.029 ns" { wb_we_i dl[2] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.029 ns" { wb_we_i wb_we_i~out0 dl[2] } { 0.000ns 0.000ns 1.709ns } { 0.000ns 0.760ns 0.560ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wb_we_i source 3.019 ns - Longest register " "Info: - Longest clock path from clock \"wb_we_i\" to source register is 3.019 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns wb_we_i 1 CLK PIN_N3 43 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_N3; Fanout = 43; CLK Node = 'wb_we_i'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { wb_we_i } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.699 ns) + CELL(0.560 ns) 3.019 ns lcr\[7\] 2 REG LC_X29_Y24_N9 17 " "Info: 2: + IC(1.699 ns) + CELL(0.560 ns) = 3.019 ns; Loc. = LC_X29_Y24_N9; Fanout = 17; REG Node = 'lcr\[7\]'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "2.259 ns" { wb_we_i lcr[7] } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 43 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 43.72 % ) " "Info: Total cell delay = 1.320 ns ( 43.72 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.699 ns ( 56.28 % ) " "Info: Total interconnect delay = 1.699 ns ( 56.28 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.019 ns" { wb_we_i lcr[7] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.019 ns" { wb_we_i wb_we_i~out0 lcr[7] } { 0.000ns 0.000ns 1.699ns } { 0.000ns 0.760ns 0.560ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.029 ns" { wb_we_i dl[2] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.029 ns" { wb_we_i wb_we_i~out0 dl[2] } { 0.000ns 0.000ns 1.709ns } { 0.000ns 0.760ns 0.560ns } } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.019 ns" { wb_we_i lcr[7] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.019 ns" { wb_we_i wb_we_i~out0 lcr[7] } { 0.000ns 0.000ns 1.699ns } { 0.000ns 0.760ns 0.560ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 43 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 226 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.820 ns" { lcr[7] dl[0]~15 dl[2] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.820 ns" { lcr[7] dl[0]~15 dl[2] } { 0.000ns 1.261ns 1.374ns } { 0.000ns 0.459ns 0.726ns } } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.029 ns" { wb_we_i dl[2] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.029 ns" { wb_we_i wb_we_i~out0 dl[2] } { 0.000ns 0.000ns 1.709ns } { 0.000ns 0.760ns 0.560ns } } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.019 ns" { wb_we_i lcr[7] } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.019 ns" { wb_we_i wb_we_i~out0 lcr[7] } { 0.000ns 0.000ns 1.699ns } { 0.000ns 0.760ns 0.560ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk register uart_transmitter:transmitter\|tf_pop register uart_transmitter:transmitter\|tf_pop 528 ps " "Info: Minimum slack time is 528 ps for clock \"clk\" between source register \"uart_transmitter:transmitter\|tf_pop\" and destination register \"uart_transmitter:transmitter\|tf_pop\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.452 ns + Shortest register register " "Info: + Shortest register to register delay is 0.452 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart_transmitter:transmitter\|tf_pop 1 REG LC_X22_Y23_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y23_N8; Fanout = 4; REG Node = 'uart_transmitter:transmitter\|tf_pop'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "../src/uart_transmitter.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_transmitter.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.452 ns) 0.452 ns uart_transmitter:transmitter\|tf_pop 2 REG LC_X22_Y23_N8 4 " "Info: 2: + IC(0.000 ns) + CELL(0.452 ns) = 0.452 ns; Loc. = LC_X22_Y23_N8; Fanout = 4; REG Node = 'uart_transmitter:transmitter\|tf_pop'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "0.452 ns" { uart_transmitter:transmitter|tf_pop uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "../src/uart_transmitter.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_transmitter.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.452 ns ( 100.00 % ) " "Info: Total cell delay = 0.452 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "0.452 ns" { uart_transmitter:transmitter|tf_pop uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "0.452 ns" { uart_transmitter:transmitter|tf_pop uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns } { 0.000ns 0.452ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.076 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.076 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 7.692 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clk\" is 7.692 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 7.692 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clk\" is 7.692 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.353 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.020 ns) 1.020 ns clk 1 CLK PIN_A15 209 " "Info: 1: + IC(0.000 ns) + CELL(1.020 ns) = 1.020 ns; Loc. = PIN_A15; Fanout = 209; CLK Node = 'clk'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.773 ns) + CELL(0.560 ns) 3.353 ns uart_transmitter:transmitter\|tf_pop 2 REG LC_X22_Y23_N8 4 " "Info: 2: + IC(1.773 ns) + CELL(0.560 ns) = 3.353 ns; Loc. = LC_X22_Y23_N8; Fanout = 4; REG Node = 'uart_transmitter:transmitter\|tf_pop'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "2.333 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "../src/uart_transmitter.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_transmitter.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.580 ns ( 47.12 % ) " "Info: Total cell delay = 1.580 ns ( 47.12 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.773 ns ( 52.88 % ) " "Info: Total interconnect delay = 1.773 ns ( 52.88 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.353 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.353 ns" { clk clk~out0 uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns 1.773ns } { 0.000ns 1.020ns 0.560ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.353 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.020 ns) 1.020 ns clk 1 CLK PIN_A15 209 " "Info: 1: + IC(0.000 ns) + CELL(1.020 ns) = 1.020 ns; Loc. = PIN_A15; Fanout = 209; CLK Node = 'clk'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.773 ns) + CELL(0.560 ns) 3.353 ns uart_transmitter:transmitter\|tf_pop 2 REG LC_X22_Y23_N8 4 " "Info: 2: + IC(1.773 ns) + CELL(0.560 ns) = 3.353 ns; Loc. = LC_X22_Y23_N8; Fanout = 4; REG Node = 'uart_transmitter:transmitter\|tf_pop'" { } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "2.333 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "../src/uart_transmitter.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_transmitter.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.580 ns ( 47.12 % ) " "Info: Total cell delay = 1.580 ns ( 47.12 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.773 ns ( 52.88 % ) " "Info: Total interconnect delay = 1.773 ns ( 52.88 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.353 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.353 ns" { clk clk~out0 uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns 1.773ns } { 0.000ns 1.020ns 0.560ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.353 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.353 ns" { clk clk~out0 uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns 1.773ns } { 0.000ns 1.020ns 0.560ns } } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.353 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.353 ns" { clk clk~out0 uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns 1.773ns } { 0.000ns 1.020ns 0.560ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns - " "Info: - Micro clock to output delay of source is 0.176 ns" { } { { "../src/uart_transmitter.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_transmitter.v" 28 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "../src/uart_transmitter.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_transmitter.v" 28 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.353 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.353 ns" { clk clk~out0 uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns 1.773ns } { 0.000ns 1.020ns 0.560ns } } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.353 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.353 ns" { clk clk~out0 uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns 1.773ns } { 0.000ns 1.020ns 0.560ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} } { { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "0.452 ns" { uart_transmitter:transmitter|tf_pop uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "0.452 ns" { uart_transmitter:transmitter|tf_pop uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns } { 0.000ns 0.452ns } } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.353 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.353 ns" { clk clk~out0 uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns 1.773ns } { 0.000ns 1.020ns 0.560ns } } } { "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii6.0/win/TimingClosureFloorplan.fld" "" "3.353 ns" { clk uart_transmitter:transmitter|tf_pop } "NODE_NAME" } } { "e:/quartusii6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartusii6.0/win/Technology_Viewer.qrui" "3.353 ns" { clk clk~out0 uart_transmitter:transmitter|tf_pop } { 0.000ns 0.000ns 1.773ns } { 0.000ns 1.020ns 0.560ns } } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
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