uart_regs.tan.qmsg

ALTER FPGA/GPLD设计（初级篇）的源码

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "wb_we_i " "Info: Assuming node \"wb_we_i\" is an undefined clock" {  } { { "../src/uart_regs.v" "" { Text "D:/Example/Example-b3-1/uart_regs/src/uart_regs.v" 19 -1 0 } } { "e:/quartusii6.0/win/Assignment Editor.qase" "" { Assignment "e:/quartusii6.0/win/Assignment Editor.qase" 1 { { 0 "wb_we_i" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}