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📄 uart_regs.sim.vwf

📁 ALTER FPGA/GPLD设计（初级篇）的源码
💻 VWF
📖 第 1 页 / 共 5 页
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TRANSITION_LIST("wb_re_i")
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}

TRANSITION_LIST("wb_rst_i")
{
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}

TRANSITION_LIST("wb_we_i")
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TRANSITION_LIST("stx_pad_o")
{
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}

TRANSITION_LIST("int_o")
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}

TRANSITION_LIST("uart_receiver:receiver|rf_push")
{
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}

TRANSITION_LIST("uart_transmitter:transmitter|bit_counter[2]")
{
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}

TRANSITION_LIST("uart_transmitter:transmitter|bit_counter[1]")
{
	NODE
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}

TRANSITION_LIST("uart_transmitter:transmitter|bit_counter[0]")
{
	NODE
	{
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}

TRANSITION_LIST("wb_dat_o[0]")
{
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			LE
12345

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