clkdiv.v

来自「Example of a FPGA memory controler」· Verilog 代码 · 共 49 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:12:58 10/04/2007 
// Design Name: 
// Module Name:    clkDiv 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module clkDiv(clkOut, clkIn);
    output clkOut;
    input clkIn;

	parameter powerOf2 = 1;
	
	generate
	
		if (powerOf2 < 1) begin
			assign clkOut = clkIn;
		end
		else if (powerOf2 == 1) begin
			reg count;
			assign clkOut = count;
			always @(posedge clkIn)
				count = ~count;
		end
		else begin
			reg [powerOf2-1:0] count;
			assign clkOut = count[powerOf2-1];
			always @(posedge clkIn)
				count = count + 1;
		end
	
	endgenerate
	

endmodule