bcd27seg.v

Example of a FPGA memory controler

`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date:    10:03:59 10/04/2007 
// Design Name: 
// Module Name:    bcd27seg 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
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module bcd27seg(segs, bcd, point, mode);
    output reg [7:0] segs;
    input [3:0] bcd;
    input point;
	 input [1:0] mode;

	 always @(*) begin
		segs[7] = ~point;						// punto
		if (mode == 2'b00) begin			// d韌ito apagado
			segs[6:0] = 7'b1111111;
		end
		else if (mode == 2'b01) begin		// signo menos
			segs[6:0] = 7'b0111111;
		end
		else begin								// d韌ito normal
			case(bcd)
				4'h0:	segs[6:0] = 7'b1000000;
				4'h1:	segs[6:0] = 7'b1111001;
				4'h2:	segs[6:0] = 7'b0100100;
				4'h3:	segs[6:0] = 7'b0110000;
				4'h4:	segs[6:0] = 7'b0011001;
				4'h5:	segs[6:0] = 7'b0010010;
				4'h6:	segs[6:0] = 7'b0000010;
				4'h7:	segs[6:0] = 7'b1111000;
				4'h8:	segs[6:0] = 7'b0000000;
				4'h9:	segs[6:0] = 7'b0010000;
				4'hA:	segs[6:0] = 7'b0001000;
				4'hB:	segs[6:0] = 7'b0000000;
				4'hC:	segs[6:0] = 7'b1000110;
				4'hD:	segs[6:0] = 7'b1000000;
				4'hE:	segs[6:0] = 7'b0000110;
				4'hF:	segs[6:0] = 7'b0001110;
			endcase
		end
	end
			

endmodule