displaydrv.v

来自「Example of a FPGA memory controler」· Verilog 代码 · 共 79 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    22:00:37 10/04/2007 
// Design Name: 
// Module Name:    anodeDrv 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision:3//
//////////////////////////////////////////////////////////////////////////////////
module displayDrv(anodes, segments, inputs, point, anyPoint, isSigned, sign, clk);
    output [3:0] anodes;
	 output [7:0] segments;
	 input [15:0] inputs;
	 input [2:0] point;
	 input anyPoint;
	 input isSigned;
	 input sign;
    input clk;
	 
	reg [1:0] cnt;
	reg [3:0] currentBCD;
	reg currentPoint;
	reg [1:0] mode;
	
	bcd27seg conv(.segs(segments), .bcd(currentBCD), .point(currentPoint), .mode(mode));
	 
	always @(posedge clk)
		cnt <= cnt + 1;

	reg [3:0] anodeReg;
	assign anodes = anodeReg;		

	always @(*) begin
		case (cnt)
			2'b00: begin
				anodeReg = 4'b1110;
				mode = 2'b11;					// d韌ito normal
				currentBCD = inputs[3:0];
			end
			2'b01: begin
				anodeReg = 4'b1101;
				mode = 2'b11;					// d韌ito normal
				currentBCD = inputs[7:4];
			end
			2'b10: begin
				anodeReg = 4'b1011;
				mode = 2'b11;					// d韌ito normal
				currentBCD = inputs[11:8];
			end
			2'b11: begin
				anodeReg = 4'b0111;
            currentBCD = inputs[15:12];
				if (!isSigned) begin
					mode = 2'b11;				// d韌ito normal
				end
				else if (sign == 0) begin
					mode = 2'b00;				// d韌ito apagado
				end
				else begin
					mode = 2'b01;				// signo menos
				end
			end
		endcase
		if (anyPoint && point == cnt)
			currentPoint = 1'b1;
		else
			currentPoint = 1'b0;
	end

endmodule