debounce.v

来自「Example of a FPGA memory controler」· Verilog 代码 · 共 37 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:27:18 10/04/2007 
// Design Name: 
// Module Name:    debounce 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module debounce(sigOut, sigIn, clock);
    output sigOut;
    input sigIn;
	 input clock;
	 
	 parameter nStages = 4;
	 
	 reg [nStages-1 : 0] shift;
	 assign sigOut = &(shift);

	always @(posedge clock) begin
		shift <= {shift[nStages-2:0], sigIn};
	end
		

endmodule