bin2bcd.v

来自「Example of a FPGA memory controler」· Verilog 代码 · 共 46 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    09:30:27 10/05/2007 
// Design Name: 
// Module Name:    bin2bcd 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module bin2bcd(Q, MODOUT, MODIN, INIT_BAR, CLK);
    output reg [3:0] Q;
    output MODOUT;
    input MODIN;
    input INIT_BAR;
    input CLK;
	 
	assign MODOUT = (Q < 5) ? 0 : 1;
	
	always @(posedge CLK) begin
		if (!INIT_BAR)
			Q <= 4'd0;
		else begin
			case (Q) 
				4'd5: Q <= {3'd0, MODIN};
				4'd6: Q <= {3'd1, MODIN};
				4'd7: Q <= {3'd2, MODIN};
				4'd8: Q <= {3'd3, MODIN};
				4'd9: Q <= {3'd4, MODIN};
				default: Q <= {Q[2:0], MODIN};
			endcase
		end
	end
			
endmodule