testmem.v

Example of a FPGA memory controler

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    09:11:11 10/12/2007 
// Design Name: 
// Module Name:    testMem 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

module testMem(clock, switches, buttons, segments, segAnodes, leds);
    input clock;
    input [7:0] switches;
	 input [3:0] buttons;
	 output [7:0] segments;
	 output [3:0] segAnodes;
    output [7:0] leds;
	 
	 parameter indexBits = 8;
	wire [7:0] mult;
	wire [15:0] AUX;
	wire clkDivided;
	wire [3:0] dbnButtons, osButtons;
	clkDiv #(.powerOf2(16)) clockDivider (.clkIn(clock), .clkOut(clkDivided));
	debounce debounce1 [3:0] (.sigOut(dbnButtons), .sigIn(buttons), .clock(clkDivided));
	oneShot oneShot1 [3:0] (.sigOut(osButtons), .sigIn(dbnButtons), .clk(clock));
	
	reg [indexBits-1:0] index;  // 韓dice de lectura y escritura a memoria
	reg signed [7:0] mem [0:2**indexBits - 1]; // memoria 
	reg signed [7:0] memIn, memOut; // registros de escritura y lectura de memoria
	reg memWE;
	wire memEN = 1;
	reg signed [7:0] A, B;
	
	always @(posedge clock) begin  // crea una instancia de block RAM
		if (memEN) begin
			if (memWE)
				mem[index] <= memIn;
			memOut <= mem[index];
		end
	end
	
	reg displaySel;
	
	assign leds[7] = displaySel;
	assign leds[6:0] = index;
	assign mult=AUX[7:0];
	assign AUX=A*B;	
	
	reg state;
	
	always @(posedge clock) begin
		case (state)
		0:	begin
			if (osButtons[0]) begin // incrementa 韓dice
				index <= index + 1;
				displaySel <= 1;
				state <= 0;
			end
			else if (osButtons[1]) begin // decrementa 韓dice
				//index <= index - 1;
				A <= switches;
				displaySel <= 1;
				state <= 0;
			end
			else if (osButtons[2]) begin // escribe en memoria
				//memIn <= switches;
				B <= switches;
				displaySel <= 1;
				memWE <= 1;
				state <= 1;
			end
			else if (osButtons[3]) begin // intercambia despliegue
				displaySel <= ~displaySel;
				state <= 0;
			end
			else 
				state <= 0;
			end
		1: begin
				memWE <= 0;
				displaySel <= 0;
				state <= 0;
			end
		endcase
	end
	
   initial
      $readmemh("mem.dat", mem);
	
	// despliegue de resultados
	
	wire [7:0] binIn = displaySel ? mult : switches; //memOut : switches;
	
	wire ready;
	wire [15:0] digits;
	bin2bcdMultidigit #(.nBits(8), .nDigits(4)) conversor (.bcd(digits), .ready(ready), 
		.bin(binIn), .load(1), .clk(clock));
	displayDrv driver(.anodes(segAnodes), .segments(segments), .inputs(digits), 
		.point(0), .anyPoint(0), .isSigned(0), .sign(0), .clk(clkDivided));	
		


endmodule