oneshot.v

来自「Example of a FPGA memory controler」· Verilog 代码 · 共 37 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    13:47:20 10/04/2007 
// Design Name: 
// Module Name:    oneShot 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module oneShot(sigOut, sigIn, clk);
    output reg sigOut;
    input sigIn;
    input clk;
	 
	reg [1:0] shift;
	 
	always @(posedge clk) begin
		shift <= {shift[0], sigIn};
		if (shift == 2'b01)
			sigOut <= 1;
		else
			sigOut <= 0;
	end
	 
endmodule