bin2bcdmultidigit.v

Example of a FPGA memory controler

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:19:42 10/05/2007 
// Design Name: 
// Module Name:    bin2bcdMultidigit 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module bin2bcdMultidigit(bcd, ready, bin, load, clk);
parameter nDigits = 4;
parameter nBits = 8;

    output reg [nDigits*4-1:0] bcd;
    output reg ready;
    input [nBits-1:0] bin;
    input load;
	 input clk;

	wire [nDigits*4-1:0] bcdTmp;
	reg [nBits-1:0] shiftReg;
	reg shift;
	wire [nDigits:0] carry;

	assign carry[0] = shiftReg[nBits-1];

	bin2bcd dig [nDigits-1:0] (.Q(bcdTmp), .MODOUT(carry[nDigits:1]), .MODIN(carry[nDigits-1:0]), 
										.INIT_BAR(shift), .CLK(clk));

	
//	bin2bcd dig0(.Q(bcdTmp[3:0]), .MODOUT(carry[1]), .MODIN(carry[0]), .INIT_BAR(shift), .CLK(clk));
//	bin2bcd dig1(.Q(bcdTmp[7:4]), .MODOUT(carry[2]), .MODIN(carry[1]), .INIT_BAR(shift), .CLK(clk));
//	bin2bcd dig2(.Q(bcdTmp[11:8]), .MODOUT(carry[3]), .MODIN(carry[2]), .INIT_BAR(shift), .CLK(clk));
	
	reg [nBits-1:0] state;
	
	always @(posedge clk) begin
		if (state == 0) begin
			if (load) begin
				shiftReg <= bin;
				shift <= 1;
				state <= 1;
				ready <= 0;
			end
			else begin
				shift <= 0;
				state <= 0;
				ready <= 0;
			end
		end
		else if (state < nBits+1) begin
			shiftReg <= shiftReg << 1;
			shift <= 1;
			ready <= 0;
			state <= state + 1;
		end
		else begin
			shift <= 0;
			state <= 0;
			ready <= 1;
			bcd <= bcdTmp;
		end
	end
		

endmodule