testdiv.v

Example of a FPGA memory controler

`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date:    13:37:55 11/13/2007 
// Design Name: 
// Module Name:    testDiv 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
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module testDiv(clock, switches, buttons, segments, segAnodes, leds);
    input clock;
    input [7:0] switches;
	 input [3:0] buttons;
	 output [7:0] segments;
	 output [3:0] segAnodes;
    output [7:0] leds;
	 
	 parameter indexBits = 4;
	wire [10:0] mult;
	wire [10:0] AUX;
	wire clkDivided;
	wire [3:0] dbnButtons, osButtons;
	clkDiv #(.powerOf2(16)) clockDivider (.clkIn(clock), .clkOut(clkDivided));
	debounce debounce1 [3:0] (.sigOut(dbnButtons), .sigIn(buttons), .clock(clkDivided));
	oneShot oneShot1 [3:0] (.sigOut(osButtons), .sigIn(dbnButtons), .clk(clock));
	
	reg signed [7:0] A, B;
	
	reg displaySel;
	reg start_div;
	assign leds[7] = displaySel;
	assign leds[6:0] = 7'd0;
	assign mult=AUX;
	wire [17:0] Ax={A,10'd0};
	wire [17:0] Bx={B,10'd0};
	wire signed [17:0] div;
	Division D1(.dividendo(Ax), .divisor(Bx), .cuociente(div),.clk(clock),.start(start_div));
	wire [35:0] AUX1=div*18'd10;
	assign AUX = {AUX1[35],AUX1[21:12]};
	reg state;
	
	always @(posedge clock) begin
		case (state)
		0:	begin
			if (osButtons[0]) begin // incrementa 韓dice
				displaySel <= 1;
				state <= 0;
				start_div<=0;
			end
			else if (osButtons[1]) begin // decrementa 韓dice
				A <= switches;
				displaySel <= 0;
				state <= 0;
				start_div<=0;
				
			end
			else if (osButtons[2]) begin // escribe en memoria
				B <= switches;
				displaySel <= 0;
				state <= 1;
				start_div<=1;
			end
			else if (osButtons[3]) begin // intercambia despliegue
				displaySel <= ~displaySel;
				state <= 0;
				start_div<=0;
			end
			else begin
				state <= 0;
				start_div<=0;
				end
			end
		1: begin
				state <= 0;
				start_div<=1;
			end
		endcase
	end
		
	// despliegue de resultados
	wire [15:0] AUX3 = switches*8'd10;
	
	wire [9:0] show1 = ~mult[10] ? mult[9:0] : ((~ mult[9:0]) + 1);
	wire [9:0] show2 = ~switches[7] ? {AUX3[11:2]} : ((~ AUX3[11:2]) + 1);
	wire [9:0] binIn = displaySel ? show1 : show2;
	wire sign = displaySel ? AUX[10] : switches[7];
	wire ready;
	wire [11:0] digits;
	bin2bcdMultidigit #(.nBits(10), .nDigits(3)) conversor (.bcd(digits), .ready(ready), 
		.bin(binIn), .load(1), .clk(clock));
	displayDrv driver(.anodes(segAnodes), .segments(segments), .inputs(digits), 
		.point(1), .anyPoint(1), .isSigned(1), .sign(sign), .clk(clkDivided));	
		


endmodule