main_ctrl.ucf

利用XC9572－PQ44（Xilinx CPLD）制作的一款家用防盗报警器的Verilog源代码及原理图

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "alert_phone"  LOC = "P40"  ; 
NET "alert_sound"  LOC = "P26"  ; 
NET "clk540hz"  LOC = "P28"  ; 
NET "clk5hz"  LOC = "P5"  ; 
NET "clk660hz"  LOC = "P20"  ; 
NET "led1"  LOC = "P4"  ; 
NET "power_ctrl"  LOC = "P42"  ; 
NET "ring_out"  LOC = "P35"  ;
NET "sw1"  LOC = "P22"  ; 

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE