📄 defeqns.htm
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<br/> OR (state(1) AND state(3) AND NOT state(0) AND NOT timer(0) AND
<br/> timer(1) AND timer(2) AND timer(3) AND timer(4) AND timer(5) AND
<br/> timer(6) AND timer(7)));
</td></tr><tr><td>
FTCPE_state2: FTCPE port map (state(2),state_T(2),NOT clk5hz,'0','0');
<br/> state_T(2) <= ((EXP6_.EXP)
<br/> OR (state(1) AND state(3) AND state(2)));
</td></tr><tr><td>
FDCPE_state3: FDCPE port map (state(3),state_D(3),NOT clk5hz,'0','0');
<br/> state_D(3) <= ((EXP28_.EXP)
<br/> OR (NOT sw1 AND state(3) AND NOT state(2))
<br/> OR (NOT state(1) AND state(3) AND NOT state(0))
<br/> OR (state(3) AND state(0) AND NOT state(2))
<br/> OR (state(3) AND NOT state(2) AND timer(1) AND timer(2) AND
<br/> timer(3) AND timer(4) AND timer(5) AND timer(6) AND timer(7))
<br/> OR (sw1 AND state(1) AND NOT state(0) AND NOT state(2) AND
<br/> NOT timer(0) AND timer(1) AND timer(2) AND NOT timer(3) AND NOT timer(4) AND
<br/> NOT timer(5) AND NOT timer(6) AND NOT timer(7)));
</td></tr><tr><td>
FTCPE_timer0: FTCPE port map (timer(0),timer_T(0),NOT clk5hz,'0','0');
<br/> timer_T(0) <= ((EXP29_.EXP)
<br/> OR (sw1 AND NOT state(1) AND NOT state(3) AND NOT state(2) AND
<br/> NOT timer(0))
<br/> OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND
<br/> NOT state(2) AND NOT timer(0) AND timer(4))
<br/> OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND
<br/> NOT state(2) AND NOT timer(0) AND timer(1) AND timer(3))
<br/> OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND
<br/> NOT state(2) AND NOT timer(0) AND NOT timer(1) AND NOT timer(3))
<br/> OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND
<br/> NOT state(2) AND NOT timer(0) AND timer(2) AND timer(3)));
</td></tr><tr><td>
FDCPE_timer1: FDCPE port map (timer(1),timer_D(1),NOT clk5hz,'0','0');
<br/> timer_D(1) <= ((timer(3).EXP)
<br/> OR (EXP12_.EXP)
<br/> OR (NOT state(1) AND NOT state(3) AND NOT state(2) AND NOT timer(1) AND
<br/> NOT timer(2) AND NOT timer(3) AND timer(4) AND timer(5) AND timer(6) AND
<br/> NOT timer(7))
<br/> OR (NOT state(3) AND state(0) AND state(2) AND timer(1) AND
<br/> NOT timer(2) AND NOT timer(3) AND NOT timer(4) AND NOT timer(5) AND NOT timer(6) AND
<br/> NOT timer(7))
<br/> OR (NOT state(3) AND NOT state(0) AND state(2) AND NOT timer(1) AND
<br/> NOT timer(2) AND NOT timer(3) AND NOT timer(4) AND NOT timer(5) AND NOT timer(6) AND
<br/> NOT timer(7))
<br/> OR (state(1) AND state(3) AND NOT state(0) AND NOT state(2) AND
<br/> timer(1) AND timer(2) AND timer(3) AND timer(4) AND timer(5) AND
<br/> timer(6) AND timer(7))
<br/> OR (state(1) AND NOT state(3) AND state(0) AND NOT state(2) AND
<br/> NOT timer(1) AND timer(2) AND timer(3) AND NOT timer(4) AND NOT timer(5) AND
<br/> NOT timer(6) AND NOT timer(7)));
</td></tr><tr><td>
FDCPE_timer2: FDCPE port map (timer(2),timer_D(2),NOT clk5hz,'0','0');
<br/> timer_D(2) <= ((EXP25_.EXP)
<br/> OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND
<br/> NOT state(2) AND timer(0))
<br/> OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND
<br/> NOT state(2) AND NOT timer(1))
<br/> OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND
<br/> NOT state(2) AND timer(4))
<br/> OR (state(1) AND state(3) AND NOT state(0) AND NOT state(2) AND
<br/> timer(1) AND timer(2) AND timer(3) AND timer(4) AND timer(5) AND
<br/> timer(6) AND timer(7))
<br/> OR (state(1) AND NOT state(3) AND state(0) AND NOT state(2) AND
<br/> timer(0) AND timer(2) AND timer(3) AND NOT timer(4) AND NOT timer(5) AND
<br/> NOT timer(6) AND NOT timer(7)));
</td></tr><tr><td>
FDCPE_timer3: FDCPE port map (timer(3),timer_D(3),NOT clk5hz,'0','0');
<br/> timer_D(3) <= ((EXP11_.EXP)
<br/> OR (state(1) AND state(3) AND NOT state(0) AND NOT state(2) AND
<br/> timer(1) AND timer(2) AND timer(3) AND timer(4) AND timer(5) AND
<br/> timer(6) AND timer(7))
<br/> OR (state(1) AND NOT state(3) AND state(0) AND NOT state(2) AND
<br/> timer(0) AND timer(2) AND timer(3) AND NOT timer(4) AND NOT timer(5) AND
<br/> NOT timer(6) AND NOT timer(7)));
</td></tr><tr><td>
FTCPE_timer4: FTCPE port map (timer(4),timer_T(4),NOT clk5hz,'0','0');
<br/> timer_T(4) <= ((EXP30_.EXP)
<br/> OR (sw1 AND NOT state(1) AND NOT state(3) AND NOT state(2) AND
<br/> timer(4))
<br/> OR (NOT sw1 AND timer(0) AND timer(1) AND timer(2) AND
<br/> timer(3))
<br/> OR (state(1) AND timer(0) AND timer(1) AND timer(2) AND
<br/> timer(3))
<br/> OR (state(3) AND timer(0) AND timer(1) AND timer(2) AND
<br/> timer(3))
<br/> OR (state(2) AND timer(0) AND timer(1) AND timer(2) AND
<br/> timer(3)));
</td></tr><tr><td>
FTCPE_timer5: FTCPE port map (timer(5),timer_T(5),NOT clk5hz,'0','0');
<br/> timer_T(5) <= ((EXP15_.EXP)
<br/> OR (state(2).EXP)
<br/> OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND
<br/> NOT state(2) AND timer(4) AND timer(5))
<br/> OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND
<br/> NOT state(2) AND timer(0) AND NOT timer(2) AND timer(5))
<br/> OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND
<br/> NOT state(2) AND NOT timer(1) AND timer(2) AND timer(5))
<br/> OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND
<br/> NOT state(2) AND NOT timer(1) AND NOT timer(3) AND timer(5))
<br/> OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND
<br/> NOT state(2) AND NOT timer(0) AND timer(2) AND timer(3) AND timer(5)));
</td></tr><tr><td>
FTCPE_timer6: FTCPE port map (timer(6),timer_T(6),NOT clk5hz,'0','0');
<br/> timer_T(6) <= ((EXP7_.EXP)
<br/> OR (EXP8_.EXP)
<br/> OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND
<br/> NOT state(2) AND timer(0) AND NOT timer(2) AND timer(6))
<br/> OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND
<br/> NOT state(2) AND NOT timer(1) AND timer(2) AND timer(6))
<br/> OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND
<br/> NOT state(2) AND NOT timer(1) AND NOT timer(3) AND timer(6))
<br/> OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND
<br/> NOT state(2) AND NOT timer(3) AND timer(4) AND timer(6))
<br/> OR (sw1 AND state(1) AND state(3) AND NOT state(0) AND
<br/> NOT state(2) AND NOT timer(0) AND timer(2) AND timer(3) AND timer(6)));
</td></tr><tr><td>
FTCPE_timer7: FTCPE port map (timer(7),timer_T(7),NOT clk5hz,'0','0');
<br/> timer_T(7) <= ((EXP13_.EXP)
<br/> OR (EXP14_.EXP)
<br/> OR (sw1 AND NOT state(1) AND NOT state(3) AND NOT state(2) AND
<br/> timer(7))
<br/> OR (NOT sw1 AND timer(0) AND timer(1) AND timer(2) AND
<br/> timer(3) AND timer(4) AND timer(5) AND timer(6))
<br/> OR (state(1) AND timer(0) AND timer(1) AND timer(2) AND
<br/> timer(3) AND timer(4) AND timer(5) AND timer(6))
<br/> OR (state(3) AND timer(0) AND timer(1) AND timer(2) AND
<br/> timer(3) AND timer(4) AND timer(5) AND timer(6))
<br/> OR (state(2) AND timer(0) AND timer(1) AND timer(2) AND
<br/> timer(3) AND timer(4) AND timer(5) AND timer(6)));
</td></tr><tr><td>
Register Legend:
<br/> FDCPE (Q,D,C,CLR,PRE,CE);
<br/> FTCPE (Q,D,C,CLR,PRE,CE);
<br/> LDCP (Q,D,G,CLR,PRE);
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