⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 defeqns.htm

📁 利用XC9572-PQ44(Xilinx CPLD)制作的一款家用防盗报警器的Verilog源代码及原理图
💻 HTM
📖 第 1 页 / 共 2 页
字号:
<html><head><link type='text/css' href='style.css' rel='stylesheet'></head><body class='pgBgnd'>
<h3 align='center'>Equations</h3>
<table width='90%' align='center' border='1' cellpadding='0' cellspacing='0'>
<tr><td>
</td></tr><tr><td>
********** Mapped Logic **********
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
</td></tr><tr><td>
FTCPE_alert_phone: FTCPE port map (alert_phone,alert_phone_T,NOT clk5hz,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;alert_phone_T <= ((EXP16_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (EXP17_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (alert_phone AND NOT state(1) AND state(3) AND state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sw1 AND alert_phone AND NOT state(1) AND NOT state(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT state(2) AND NOT timer(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sw1 AND alert_phone AND NOT state(1) AND NOT state(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT state(2) AND timer(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sw1 AND alert_phone AND NOT state(1) AND NOT state(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT state(2) AND timer(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sw1 AND alert_phone AND NOT state(1) AND NOT state(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT state(2) AND timer(3)));
</td></tr><tr><td>
FTCPE_alert_sound: FTCPE port map (alert_sound,alert_sound_T,NOT clk5hz,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;alert_sound_T <= ((EXP23_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (EXP24_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sw1 AND alert_sound AND NOT state(1) AND NOT state(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT state(2) AND NOT timer(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sw1 AND alert_sound AND NOT state(1) AND NOT state(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT state(2) AND timer(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sw1 AND alert_sound AND NOT state(1) AND NOT state(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT state(2) AND timer(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sw1 AND alert_sound AND NOT state(1) AND NOT state(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT state(2) AND timer(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sw1 AND alert_sound AND NOT state(1) AND NOT state(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(0) AND NOT state(2) AND NOT timer(4)));
</td></tr><tr><td>
FDCPE_led1: FDCPE port map (led1,EXP10_.EXP,NOT clk5hz,'0','0');
</td></tr><tr><td>
FDCPE_power_ctrl: FDCPE port map (power_ctrl,power_ctrl_D,NOT clk5hz,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;power_ctrl_D <= ((EXP18_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (EXP19_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (sw1 AND NOT power_ctrl)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT power_ctrl AND state(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT power_ctrl AND state(3))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT power_ctrl AND state(0))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT power_ctrl AND state(2)));
</td></tr><tr><td>
FTCPE_ring_en: FTCPE port map (ring_en,ring_en_T,NOT clk5hz,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;ring_en_T <= ((EXP20_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (EXP21_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(1) AND state(3) AND state(0) AND NOT state(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	ring_en)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sw1 AND NOT state(1) AND NOT state(3) AND NOT state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(2) AND NOT timer(0) AND ring_en)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sw1 AND NOT state(1) AND NOT state(3) AND NOT state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(2) AND ring_en AND timer(1))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sw1 AND NOT state(1) AND NOT state(3) AND NOT state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(2) AND ring_en AND timer(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sw1 AND NOT state(1) AND NOT state(3) AND NOT state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(2) AND ring_en AND timer(3)));
</td></tr><tr><td>
</td></tr><tr><td>
ring_out_I <= ((clk5hz AND clk660hz)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT clk5hz AND clk540hz));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;ring_out <= ring_out_I when ring_out_OE = '1' else 'Z';
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;ring_out_OE <= ring_en;
</td></tr><tr><td>
FTCPE_state0: FTCPE port map (state(0),state_T(0),NOT clk5hz,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;state_T(0) <= ((EXP26_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (EXP27_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (sw1 AND NOT state(1) AND NOT state(3) AND state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(1) AND NOT state(3) AND NOT state(2) AND timer(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT timer(1) AND NOT timer(2) AND NOT timer(3) AND timer(4) AND timer(5) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	timer(6) AND NOT timer(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT state(1) AND state(0) AND state(2) AND NOT timer(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	timer(1) AND NOT timer(2) AND NOT timer(3) AND NOT timer(4) AND NOT timer(5) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT timer(6) AND NOT timer(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (state(1) AND NOT state(3) AND state(0) AND NOT state(2) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	timer(0) AND NOT timer(1) AND timer(2) AND timer(3) AND NOT timer(4) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT timer(5) AND NOT timer(6) AND NOT timer(7))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (sw1 AND state(1) AND NOT state(3) AND NOT state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(2) AND NOT timer(0) AND timer(1) AND timer(2) AND NOT timer(3) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT timer(4) AND NOT timer(5) AND NOT timer(6) AND NOT timer(7)));
</td></tr><tr><td>
FTCPE_state1: FTCPE port map (state(1),state_T(1),NOT clk5hz,'0','0');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;state_T(1) <= ((EXP22_.EXP)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (state(1) AND state(3) AND state(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (sw1 AND NOT state(1) AND NOT state(3) AND NOT state(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT sw1 AND state(1) AND NOT state(3) AND NOT state(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT state(2))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (state(1) AND state(3) AND state(0) AND timer(0) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT timer(1) AND NOT timer(2) AND NOT timer(3) AND NOT timer(4) AND NOT timer(5) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT timer(6) AND NOT timer(7))

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -