main_ctrl.gyd

利用XC9572－PQ44（Xilinx CPLD）制作的一款家用防盗报警器的Verilog源代码及原理图

Pin Freeze File:  version I.27

9572XL44PC XC9572XL-5-PC44
clk540hz S:PIN28
clk5hz S:PIN5
clk660hz S:PIN20
sw1 S:PIN22
alert_phone S:PIN40
alert_sound S:PIN26
led1 S:PIN4
power_ctrl S:PIN42
ring_out S:PIN35


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.

PARTITION FB1_1 EXP6_ EXP7_ timer<6> EXP8_
		
PARTITION FB1_6 EXP9_ EXP10_ led1_OBUF EXP11_
		 timer<3> timer<1> EXP12_ EXP13_
		 timer<7> EXP14_ EXP15_ timer<5>
		 state<2>
PARTITION FB2_2 ring_out_OBUFE
PARTITION FB2_10 EXP16_ alert_phone_OBUF EXP17_ EXP18_
		 power_ctrl_OBUF EXP19_

PARTITION FB3_16 EXP20_ ring_en EXP21_
PARTITION FB4_1 EXP22_ state<1>
PARTITION FB4_4 EXP23_ alert_sound_OBUF EXP24_ EXP25_
		 timer<2>
PARTITION FB4_10 EXP26_ state<0> EXP27_ state<3>
		 EXP28_ timer<0> EXP29_ EXP30_
		 timer<4>