main_ctrl.syr

利用XC9572－PQ44（Xilinx CPLD）制作的一款家用防盗报警器的Verilog源代码及原理图

Release 8.1.03i - xst I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: main_ctrl.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "main_ctrl.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "main_ctrl"
Output Format                      : NGC
Target Device                      : XC9500XL CPLDs

---- Source Options
Top Module Name                    : main_ctrl
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : main_ctrl.lso
verilog2001                        : YES
safe_implementation                : No
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "main-ctrl.v" in library work
Module <main_ctrl> compiled
No errors in compilation
Analysis of file <"main_ctrl.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <main_ctrl>.
	count15s = 32'sb00000000000000000000000001110010
	count2s = 32'sb00000000000000000000000000000111
	delay_15s = 32'sb00000000000000000000000000000000
	delay_15s2 = 32'sb00000000000000000000000000000001
	sw1_detect = 32'sb00000000000000000000000000000010
	alert1 = 32'sb00000000000000000000000000000011
	alert2 = 32'sb00000000000000000000000000000100
	alert3 = 32'sb00000000000000000000000000000101
	alert4 = 32'sb00000000000000000000000000000110
	alert5 = 32'sb00000000000000000000000000000111
	sound = 32'sb00000000000000000000000000001000
	power_off = 32'sb00000000000000000000000000001001
	alert_ring = 32'sb00000000000000000000000000001010
	sound1 = 32'sb00000000000000000000000000001011
	sound2 = 32'sb00000000000000000000000000001100
	sound3 = 32'sb00000000000000000000000000001101
Module <main_ctrl> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <main_ctrl>.
    Related source file is "main-ctrl.v".
    Found 1-bit register for signal <led1>.
    Found 1-bit tristate buffer for signal <ring_out>.
    Found 1-bit register for signal <alert_phone>.
    Found 1-bit register for signal <alert_sound>.
    Found 1-bit register for signal <power_ctrl>.
    Found 8-bit adder for signal <$n0023> created at line 59.
    Found 1-bit register for signal <ring_en>.
    Found 4-bit register for signal <state>.
    Found 8-bit register for signal <timer>.
    Summary:
	inferred   5 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Tristate(s).
Unit <main_ctrl> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 8-bit adder                                           : 1
# Registers                                            : 7
 1-bit register                                        : 5
 4-bit register                                        : 1
 8-bit register                                        : 1
# Tristates                                            : 1
 1-bit tristate buffer                                 : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 8-bit adder                                           : 1
# Registers                                            : 17
 Flip-Flops                                            : 17

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <main_ctrl> ...
  implementation constraint: INIT=r	 : timer_7
  implementation constraint: INIT=r	 : alert_phone
  implementation constraint: INIT=r	 : led1
  implementation constraint: INIT=r	 : state_3
  implementation constraint: INIT=s	 : power_ctrl
  implementation constraint: INIT=r	 : alert_sound
  implementation constraint: INIT=r	 : ring_en
  implementation constraint: INIT=r	 : timer_6
  implementation constraint: INIT=r	 : timer_5
  implementation constraint: INIT=r	 : state_0
  implementation constraint: INIT=r	 : state_1
  implementation constraint: INIT=r	 : state_2
  implementation constraint: INIT=r	 : timer_4
  implementation constraint: INIT=r	 : timer_0
  implementation constraint: INIT=r	 : timer_1
  implementation constraint: INIT=r	 : timer_2
  implementation constraint: INIT=r	 : timer_3

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : main_ctrl.ngr
Top Level Output File Name         : main_ctrl
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : YES
Target Technology                  : XC9500XL CPLDs
Macro Preserve                     : YES
XOR Preserve                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 9

Cell Usage :
# BELS                             : 587
#      AND2                        : 172
#      AND3                        : 31
#      AND4                        : 19
#      AND8                        : 3
#      INV                         : 252
#      OR2                         : 80
#      OR3                         : 17
#      OR4                         : 3
#      OR5                         : 1
#      OR7                         : 1
#      XOR2                        : 8
# FlipFlops/Latches                : 17
#      FD                          : 17
# IO Buffers                       : 9
#      IBUF                        : 4
#      OBUF                        : 4
#      OBUFE                       : 1
=========================================================================
CPU : 5.61 / 5.95 s | Elapsed : 5.00 / 6.00 s
 
--> 

Total memory usage is 91872 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)