hdpdeps.ref

this is the vhdl code of arithmetic and logic unit of 16 bit microprocessor.

V1 32
FL c:/xilinx/bin/microprocessor/../alu/alu.vhd 2007/06/29.23:06:29
EN work/ALU             FL c:/xilinx/bin/microprocessor/../alu/alu.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED \
      PH work/MAINPACK
AR work/ALU/ALU         FL c:/xilinx/bin/microprocessor/../alu/alu.vhd \
      EN work/ALU
FL c:/xilinx/bin/microprocessor/../../../trireg/trireg.vhd 2007/06/29.23:09:21
EN work/TRIREG          FL c:/xilinx/bin/microprocessor/../../../trireg/trireg.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/TRIREG/TRIREG   FL c:/xilinx/bin/microprocessor/../../../trireg/trireg.vhd \
      EN work/TRIREG
FL c:/xilinx/bin/microprocessor/microprocessor.vhd 2007/06/29.23:37:08
PH work/MAINPACK        FL c:/xilinx/bin/microprocessor/microprocessor.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
EN work/MICROPROCESSOR  FL c:/xilinx/bin/microprocessor/microprocessor.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED \
      PH work/MAINPACK
AR work/MICROPROCESSOR/MICROPROCESSOR \
      FL c:/xilinx/bin/microprocessor/microprocessor.vhd EN work/MICROPROCESSOR \
      CP ALU            CP SHIFT          CP TRIREG         CP COMPARATOR \
      CP REGARRAY       CP BIREG          CP CONTROL
FL c:/xilinx/bin/microprocessor/../comparator/comparator.vhd 2007/06/29.23:09:54
EN work/COMPARATOR      FL c:/xilinx/bin/microprocessor/../comparator/comparator.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED \
      PH work/MAINPACK
AR work/COMPARATOR/COMP \
      FL c:/xilinx/bin/microprocessor/../comparator/comparator.vhd \
      EN work/COMPARATOR
FL c:/xilinx/bin/microprocessor/../bireg/bireg.vhd 2007/06/29.23:08:41
EN work/BIREG           FL c:/xilinx/bin/microprocessor/../bireg/bireg.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/BIREG/BIREG     FL c:/xilinx/bin/microprocessor/../bireg/bireg.vhd \
      EN work/BIREG
FL c:/xilinx/bin/microprocessor/../control/control.vhd 2007/06/29.23:22:20
EN work/CONTROL         FL c:/xilinx/bin/microprocessor/../control/control.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED \
      PH work/MAINPACK
AR work/CONTROL/CONTROL FL c:/xilinx/bin/microprocessor/../control/control.vhd \
      EN work/CONTROL
FL c:/xilinx/bin/microprocessor/../../regarray/regarray.vhd 2007/06/29.23:07:15
EN work/REGARRAY        FL c:/xilinx/bin/microprocessor/../../regarray/regarray.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED \
      PH work/MAINPACK
AR work/REGARRAY/REGARRAY \
      FL c:/xilinx/bin/microprocessor/../../regarray/regarray.vhd \
      EN work/REGARRAY
FL c:/xilinx/bin/microprocessor/../shift/shift.vhd 2007/06/29.23:06:58
EN work/SHIFT           FL c:/xilinx/bin/microprocessor/../shift/shift.vhd \
      PB ieee/STD_LOGIC_1164 PH work/MAINPACK
AR work/SHIFT/SHIFT     FL c:/xilinx/bin/microprocessor/../shift/shift.vhd \
      EN work/SHIFT